- mt7623 update nodes to binding description
- mt2701 add display pwn nodes - mt2701 update audio node description -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAln7Z9YXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00P33RAAm5rCbd+yCz1/ymaNRX+vWEAy PbMXS+gs3dimwOp9cRmaYWzwxNG/NhyaQZAfqbgL6I5ArgvebQ+Db1N49JB/FHFP ALlfO2uPODJdIqbTIPJXLs1Wlssf2Y6B5iLoNegKJ3HCB0Ty/TcMu27NJPyu0hwv rArvf4k7zxa7kOtY2vI77nH/AheO7GXNg09/W70aZ42RkuIGdFosfCfWAK9twoz9 NxmWWvzj5G/JmY5z4FLrr5jbgAi0PMr8JfrXchWP6Jw58291ZHGtemRUxfJJuOmI ub3UyCiWWyR+jtGp7R5OgNrI5XUxWmdvuzklnLpeGekFDMEuXxPYvxRz7A5OEKLr IYlokcJsrxmZUoQGmSzpQ86MndTmdPjH3dZxTQnK2mlf9RmRGhnHq/op0no862Vj 2B99NzOltthjDjKzRNJh0VxEhrkZ8fB5Vz7ifLWCypFQ09VHCY4wHH+lMQzdf6tD FkTTbeVWMQudjgFKrfTGZYGrDGD9oe6yPidaQ2adDKkjdYGTApP4rdFWTuQm7qMT X8dLI2lj7eWo06nx0/LeBLpMe45xjCT9NmIhBi0tgKwi6yiiNe/Jk/VDc1Un7YA9 /7fTCsF21OYlOcypBo/uLdN0kVc5+Gj1j3JcgGvzcF/0edH+tKn8SfFKnJJDA0y4 SXUTFP1ShF/8zYCGpnQ= =Vfdp -----END PGP SIGNATURE----- Merge tag 'v4.14-next-dts32-2' of https://github.com/mbgg/linux-mediatek into next/dt Pull "Mediatek: 32-bit DTS updates for v4.15" from Matthias Brugger: - mt7623 update nodes to binding description - mt2701 add display pwn nodes - mt2701 update audio node description * tag 'v4.14-next-dts32-2' of https://github.com/mbgg/linux-mediatek: arm: dts: mt7623: remove unused compatible string for pio node arm: dts: mt7623: update usb related nodes arm: dts: mt7623: update crypto node arm: dts: mediatek: update audio node for mt2701 and mt7623 arm: dts: mt2701: enable display pwm backlight arm: dts: mt2701: add pwm backlight device node
This commit is contained in:
Arnd Bergmann
commit
9c7f85ad3f
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@ -56,12 +56,29 @@
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bt_sco_codec:bt_sco_codec {
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compatible = "linux,bt-sco";
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};
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backlight_lcd: backlight_lcd {
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compatible = "pwm-backlight";
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pwms = <&bls 0 100000>;
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brightness-levels = <
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0 16 32 48 64 80 96 112
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128 144 160 176 192 208 224 240
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255
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>;
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default-brightness-level = <9>;
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};
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};
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&auxadc {
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status = "okay";
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};
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&bls {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_bls_gpio>;
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins_a>;
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@ -111,6 +128,12 @@
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};
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};
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pwm_bls_gpio: pwm_bls_gpio {
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pins_cmd_dat {
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pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>;
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};
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};
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spi_pins_a: spi0@0 {
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pins_spi {
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pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
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@ -430,7 +430,9 @@
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compatible = "mediatek,mt2701-audio";
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reg = <0 0x11220000 0 0x2000>,
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<0 0x112a0000 0 0x20000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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@ -530,6 +532,15 @@
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#clock-cells = <1>;
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};
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bls: pwm@1400a000 {
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compatible = "mediatek,mt2701-disp-pwm";
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reg = <0 0x1400a000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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larb0: larb@14010000 {
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compatible = "mediatek,mt2701-smi-larb";
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reg = <0 0x14010000 0 0x1000>;
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@ -227,8 +227,7 @@
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt7623-pinctrl",
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"mediatek,mt2701-pinctrl";
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compatible = "mediatek,mt7623-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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@ -544,7 +543,9 @@
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"mediatek,mt2701-audio";
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reg = <0 0x11220000 0 0x2000>,
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<0 0x112a0000 0 0x20000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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@ -678,7 +679,7 @@
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "sys_ck", "free_ck";
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clock-names = "sys_ck", "ref_ck";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
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phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
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status = "disabled";
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@ -688,8 +689,6 @@
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compatible = "mediatek,mt7623-u3phy",
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"mediatek,mt2701-u3phy";
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reg = <0 0x1a1c4000 0 0x0700>;
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clocks = <&clk26m>;
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clock-names = "u3phya_ref";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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@ -697,12 +696,16 @@
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u2port0: usb-phy@1a1c4800 {
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reg = <0 0x1a1c4800 0 0x0100>;
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clocks = <&topckgen CLK_TOP_USB_PHY48M>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port0: usb-phy@1a1c4900 {
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reg = <0 0x1a1c4900 0 0x0700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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@ -717,7 +720,7 @@
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "sys_ck", "free_ck";
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clock-names = "sys_ck", "ref_ck";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
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phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
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status = "disabled";
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@ -727,8 +730,6 @@
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compatible = "mediatek,mt7623-u3phy",
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"mediatek,mt2701-u3phy";
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reg = <0 0x1a244000 0 0x0700>;
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clocks = <&clk26m>;
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clock-names = "u3phya_ref";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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@ -736,12 +737,16 @@
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u2port1: usb-phy@1a244800 {
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reg = <0 0x1a244800 0 0x0100>;
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clocks = <&topckgen CLK_TOP_USB_PHY48M>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port1: usb-phy@1a244900 {
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reg = <0 0x1a244900 0 0x0700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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@ -782,16 +787,15 @@
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};
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crypto: crypto@1b240000 {
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compatible = "mediatek,mt7623-crypto";
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compatible = "mediatek,eip97-crypto";
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reg = <0 0x1b240000 0 0x20000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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<ðsys CLK_ETHSYS_CRYPTO>;
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clock-names = "ethif","cryp";
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clocks = <ðsys CLK_ETHSYS_CRYPTO>;
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clock-names = "cryp";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
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status = "disabled";
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};
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