Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
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commit
9c861f3328
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@ -22,7 +22,8 @@ Required properties :
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- #clock-cells : must contain 1
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- #reset-cells : must contain 1
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For the PRCM CCUs on H3/A64, one more clock is needed:
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For the PRCM CCUs on H3/A64, two more clocks are needed:
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- "pll-periph": the SoC's peripheral PLL from the main CCU
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- "iosc": the SoC's internal frequency oscillator
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Example for generic CCU:
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@ -39,8 +40,8 @@ Example for PRCM CCU:
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r_ccu: clock@01f01400 {
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compatible = "allwinner,sun50i-a64-r-ccu";
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reg = <0x01f01400 0x100>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>;
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clock-names = "hosc", "losc", "iosc";
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clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;
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clock-names = "hosc", "losc", "iosc", "pll-periph";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -156,6 +156,7 @@ config SUN8I_R_CCU
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bool "Support for Allwinner SoCs' PRCM CCUs"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_GATE
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select SUNXI_CCU_MP
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default MACH_SUN8I || (ARCH_SUNXI && ARM64)
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endif
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@ -31,7 +31,9 @@
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#define CLK_PLL_VIDEO0_2X 8
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#define CLK_PLL_VE 9
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#define CLK_PLL_DDR0 10
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#define CLK_PLL_PERIPH0 11
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/* PLL_PERIPH0 exported for PRCM */
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#define CLK_PLL_PERIPH0_2X 12
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#define CLK_PLL_PERIPH1 13
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#define CLK_PLL_PERIPH1_2X 14
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@ -556,7 +556,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
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0x12c, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
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0x12c, 0, 4, 24, 3, BIT(31),
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0x130, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
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@ -29,7 +29,9 @@
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#define CLK_PLL_VIDEO 6
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#define CLK_PLL_VE 7
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#define CLK_PLL_DDR 8
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#define CLK_PLL_PERIPH0 9
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/* PLL_PERIPH0 exported for PRCM */
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#define CLK_PLL_PERIPH0_2X 10
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#define CLK_PLL_GPU 11
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#define CLK_PLL_PERIPH1 12
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@ -537,7 +537,7 @@ static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
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[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
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[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
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[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
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[RST_BUS_OTG] = { 0x2c0, BIT(23) },
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[RST_BUS_OTG] = { 0x2c0, BIT(24) },
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[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
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[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
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@ -43,6 +43,8 @@
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#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
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#define _DT_BINDINGS_CLK_SUN50I_A64_H_
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#define CLK_PLL_PERIPH0 11
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#define CLK_BUS_MIPI_DSI 28
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#define CLK_BUS_CE 29
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#define CLK_BUS_DMA 30
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@ -43,6 +43,8 @@
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#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
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#define _DT_BINDINGS_CLK_SUN8I_H3_H_
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#define CLK_PLL_PERIPH0 9
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#define CLK_CPUX 14
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#define CLK_BUS_CE 20
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