[TG3]: Add management FW version to ethtool report
This patch appends the management firmware version to the bootcode firmware string reported through ethtool. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -10821,9 +10821,24 @@ out_not_found:
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strcpy(tp->board_part_number, "none");
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}
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static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
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{
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u32 val;
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if (tg3_nvram_read_swab(tp, offset, &val) ||
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(val & 0xfc000000) != 0x0c000000 ||
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tg3_nvram_read_swab(tp, offset + 4, &val) ||
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val != 0)
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return 0;
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return 1;
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}
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static void __devinit tg3_read_fw_ver(struct tg3 *tp)
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{
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u32 val, offset, start;
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u32 ver_offset;
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int i, bcnt;
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if (tg3_nvram_read_swab(tp, 0, &val))
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return;
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@ -10836,29 +10851,71 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
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return;
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offset = tg3_nvram_logical_addr(tp, offset);
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if (tg3_nvram_read_swab(tp, offset, &val))
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if (!tg3_fw_img_is_valid(tp, offset) ||
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tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
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return;
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if ((val & 0xfc000000) == 0x0c000000) {
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u32 ver_offset, addr;
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int i;
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if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
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tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
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offset = offset + ver_offset - start;
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for (i = 0; i < 16; i += 4) {
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if (tg3_nvram_read(tp, offset + i, &val))
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return;
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if (val != 0)
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return;
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addr = offset + ver_offset - start;
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for (i = 0; i < 16; i += 4) {
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if (tg3_nvram_read(tp, addr + i, &val))
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return;
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val = cpu_to_le32(val);
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memcpy(tp->fw_ver + i, &val, 4);
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}
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val = le32_to_cpu(val);
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memcpy(tp->fw_ver + i, &val, 4);
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}
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if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
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(tp->tg3_flags & TG3_FLG3_ENABLE_APE))
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return;
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for (offset = TG3_NVM_DIR_START;
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offset < TG3_NVM_DIR_END;
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offset += TG3_NVM_DIRENT_SIZE) {
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if (tg3_nvram_read_swab(tp, offset, &val))
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return;
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if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
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break;
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}
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if (offset == TG3_NVM_DIR_END)
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return;
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
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start = 0x08000000;
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else if (tg3_nvram_read_swab(tp, offset - 4, &start))
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return;
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if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
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!tg3_fw_img_is_valid(tp, offset) ||
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tg3_nvram_read_swab(tp, offset + 8, &val))
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return;
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offset += val - start;
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bcnt = strlen(tp->fw_ver);
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tp->fw_ver[bcnt++] = ',';
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tp->fw_ver[bcnt++] = ' ';
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for (i = 0; i < 4; i++) {
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if (tg3_nvram_read(tp, offset, &val))
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return;
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val = le32_to_cpu(val);
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offset += sizeof(val);
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if (bcnt > TG3_VER_SIZE - sizeof(val)) {
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memcpy(&tp->fw_ver[bcnt], &val, TG3_VER_SIZE - bcnt);
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break;
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}
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memcpy(&tp->fw_ver[bcnt], &val, sizeof(val));
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bcnt += sizeof(val);
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}
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tp->fw_ver[TG3_VER_SIZE - 1] = 0;
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}
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static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
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@ -1540,6 +1540,12 @@
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#define TG3_EEPROM_MAGIC_HW 0xabcd
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#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
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#define TG3_NVM_DIR_START 0x18
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#define TG3_NVM_DIR_END 0x78
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#define TG3_NVM_DIRENT_SIZE 0xc
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#define TG3_NVM_DIRTYPE_SHIFT 24
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#define TG3_NVM_DIRTYPE_ASFINI 1
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/* 32K Window into NIC internal memory */
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#define NIC_SRAM_WIN_BASE 0x00008000
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@ -2418,7 +2424,8 @@ struct tg3 {
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u32 pci_cmd;
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char board_part_number[24];
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char fw_ver[16];
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#define TG3_VER_SIZE 32
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char fw_ver[TG3_VER_SIZE];
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u32 nic_sram_data_cfg;
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u32 pci_clock_ctrl;
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struct pci_dev *pdev_peer;
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