qcom: ipq4019: add DMA nodes to ipq4019 SoC and DK01 device tree
This adds the blsp_dma node to the device tree and the required properties for using DMA with serial Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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@ -72,6 +72,10 @@
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};
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};
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};
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};
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blsp_dma: dma@7884000 {
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status = "ok";
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};
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spi_0: spi@78b5000 {
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spi_0: spi@78b5000 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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pinctrl-names = "default";
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@ -123,6 +123,17 @@
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interrupts = <0 208 0>;
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interrupts = <0 208 0>;
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};
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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status = "disabled";
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};
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spi_0: spi@78b5000 {
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spi_0: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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reg = <0x78b5000 0x600>;
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@ -224,6 +235,8 @@
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-names = "core", "iface";
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dmas = <&blsp_dma 1>, <&blsp_dma 0>;
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dma-names = "rx", "tx";
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};
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};
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serial@78b0000 {
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serial@78b0000 {
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@ -234,6 +247,8 @@
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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clock-names = "core", "iface";
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dmas = <&blsp_dma 3>, <&blsp_dma 2>;
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dma-names = "rx", "tx";
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};
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};
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watchdog@b017000 {
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watchdog@b017000 {
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