[ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail
This patch implements the recommended workaround for erratum 411920 (ARM1136, ARM1156, ARM1176). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -740,6 +740,15 @@ if !MMU
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source "arch/arm/Kconfig-nommu"
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endif
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config ARM_ERRATA_411920
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bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
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depends on CPU_V6 && !SMP
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help
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Invalidation of the Instruction Cache operation can
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fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
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It does not affect the MPCore. This option enables the ARM Ltd.
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recommended workaround.
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endmenu
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source "arch/arm/common/Kconfig"
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@ -20,6 +20,31 @@
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#define D_CACHE_LINE_SIZE 32
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#define BTB_FLUSH_SIZE 8
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#ifdef CONFIG_ARM_ERRATA_411920
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/*
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* Invalidate the entire I cache (this code is a workaround for the ARM1136
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* erratum 411920 - Invalidate Instruction Cache operation can fail. This
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* erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
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*
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* Registers:
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* r0 - set to 0
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* r1 - corrupted
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*/
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ENTRY(v6_icache_inval_all)
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mov r0, #0
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mrs r1, cpsr
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cpsid ifa @ disable interrupts
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mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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msr cpsr_cx, r1 @ restore interrupts
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.rept 11 @ ARM Ltd recommends at least
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nop @ 11 NOPs
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.endr
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mov pc, lr
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#endif
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/*
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* v6_flush_cache_all()
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*
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@ -31,7 +56,11 @@ ENTRY(v6_flush_kern_cache_all)
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mov r0, #0
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
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#ifndef CONFIG_ARM_ERRATA_411920
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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#else
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b v6_icache_inval_all
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#endif
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#else
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mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
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#endif
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@ -103,7 +132,11 @@ ENTRY(v6_coherent_user_range)
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mov r0, #0
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#ifdef HARVARD_CACHE
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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#ifndef CONFIG_ARM_ERRATA_411920
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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#else
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b v6_icache_inval_all
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#endif
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#else
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
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#endif
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@ -18,6 +18,10 @@
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#include "mm.h"
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#ifdef CONFIG_ARM_ERRATA_411920
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extern void v6_icache_inval_all(void);
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#endif
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#ifdef CONFIG_CPU_CACHE_VIPT
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#define ALIAS_FLUSH_START 0xffff4000
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@ -32,10 +36,15 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
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asm( "mcrr p15, 0, %1, %0, c14\n"
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" mcr p15, 0, %2, c7, c10, 4\n"
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#ifndef CONFIG_ARM_ERRATA_411920
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" mcr p15, 0, %2, c7, c5, 0\n"
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#endif
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:
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: "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
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: "cc");
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#ifdef CONFIG_ARM_ERRATA_411920
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v6_icache_inval_all();
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#endif
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}
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void flush_cache_mm(struct mm_struct *mm)
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@ -48,11 +57,16 @@ void flush_cache_mm(struct mm_struct *mm)
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if (cache_is_vipt_aliasing()) {
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asm( "mcr p15, 0, %0, c7, c14, 0\n"
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" mcr p15, 0, %0, c7, c10, 4\n"
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#ifndef CONFIG_ARM_ERRATA_411920
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" mcr p15, 0, %0, c7, c5, 0\n"
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" mcr p15, 0, %0, c7, c10, 4"
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#endif
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:
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: "r" (0)
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: "cc");
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#ifdef CONFIG_ARM_ERRATA_411920
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v6_icache_inval_all();
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#endif
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}
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}
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@ -67,11 +81,16 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
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if (cache_is_vipt_aliasing()) {
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asm( "mcr p15, 0, %0, c7, c14, 0\n"
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" mcr p15, 0, %0, c7, c10, 4\n"
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#ifndef CONFIG_ARM_ERRATA_411920
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" mcr p15, 0, %0, c7, c5, 0\n"
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" mcr p15, 0, %0, c7, c10, 4"
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#endif
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:
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: "r" (0)
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: "cc");
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#ifdef CONFIG_ARM_ERRATA_411920
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v6_icache_inval_all();
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#endif
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}
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}
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