clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
Since hclk_sd and pclk_ddr source clock from CPLL or GPLL, and these two PLL may change their frequency. If we do not assign right id to pclk_ddr and hclk_sd, they will alway use default cur register value, and may get the frequency exceed their signed off frequency. So assign correct Id for them, then we can assign frequency for them in dts. Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
parent
0d92d1802c
commit
9dc486fdf6
|
@ -671,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
|
|||
RK3399_CLKGATE_CON(9), 7, GFLAGS,
|
||||
&rk3399_uart3_fracmux),
|
||||
|
||||
COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
|
||||
COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
|
||||
RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3399_CLKGATE_CON(3), 4, GFLAGS),
|
||||
|
||||
|
@ -887,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
|
|||
RK3399_CLKGATE_CON(31), 8, GFLAGS),
|
||||
|
||||
/* sdio & sdmmc */
|
||||
COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
|
||||
COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
|
||||
RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3399_CLKGATE_CON(12), 13, GFLAGS),
|
||||
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
|
||||
|
|
Loading…
Reference in a new issue