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MLK-12699-1 ARM: imx7d: clk: add two clocks definition for pxp 

The pxp require two clocks to enable when it works, and
they are 'ipg' and 'axi' clocks. Besides, the two clocks
share the same CCGR to control clock gating.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
wifi-calibration
Fancy Fang 2016-04-15 18:11:51 +08:00 committed by Frank Li
parent 2b25e7d3af
commit 9e04de3451
2 changed files with 7 additions and 1 deletions
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4
arch/arm/mach-imx/clk-imx7d.c
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@ -376,6 +376,8 @@ static u32 share_count_sai1;
static u32 share_count_sai2;
static u32 share_count_sai3;
static u32 share_count_pxp;
static struct clk_div_table test_div_table[] = {
{ .val = 3, .div = 1, },
{ .val = 2, .div = 1, },
@ -862,6 +864,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0);
clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0);
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
clks[IMX7D_PXP_IPG_CLK] = imx_clk_gate2_shared2("pxp_ipg_clk", "ipg_root_clk", base + 0x44c0, 0, &share_count_pxp);
clks[IMX7D_PXP_AXI_CLK] = imx_clk_gate2_shared2("pxp_axi_clk", "main_axi_root_clk", base + 0x44c0, 0, &share_count_pxp);
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);

4
include/dt-bindings/clock/imx7d-clock.h
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@ -449,5 +449,7 @@
#define IMX7D_CAAM_CLK 436
#define IMX7D_OCOTP_CLK 437
#define IMX7D_ADC_ROOT_CLK 438
#define IMX7D_END_CLK 439
#define IMX7D_PXP_IPG_CLK 439
#define IMX7D_PXP_AXI_CLK 440
#define IMX7D_END_CLK 441
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */