MLK-16671-1 - [i.MX8QXP/Malone]: Add vpu malone decoder driver
Integrate amphion release kernel functions Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>pull/10/head
Zhou Peng-B04994
Jason Liu
parent
bc45c851b5
commit
9e15be7678
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#
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# Codec configuration
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#
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menu "MXC VPU(Video Processing Unit) MALONE support"
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config MXC_VPU_MALONE
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tristate "Support for MXC VPU(Video Processing Unit) MALONE"
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default y
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---help---
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The VPU codec device provides codec function for H.265/H.264/MPEG4/H.263 etc.
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config MXC_VPU_MALONE_DEBUG
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bool "MXC VPU MALONE debugging"
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depends on MXC_VPU_MALONE != n
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help
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This is an option for the developers; most people should
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say N here. This enables MXC VPU driver debugging.
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endmenu
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@ -0,0 +1,197 @@
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#
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# Makefile for VPU driver.
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#
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MALONE_ROOT = $(srctree)/drivers/mxc/vpu-malone/Malone_Firmware
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#---------------------------------------------------------------------------
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# Header Include Paths
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MALONE_KERN_HEADER = \
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-I$(MALONE_ROOT)/DecKLib/KernelIF \
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-I$(MALONE_ROOT)/DecKLib/Control \
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-I$(MALONE_ROOT)/DecKLib/Incl
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SYS_HEADER = -I$(MALONE_ROOT)/Incl \
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-I$(MALONE_ROOT)/PAL/Incl \
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-I$(srctree)/drivers/mxc/vpu-malone
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MALONE_KERN_HEADER += $(SYS_HEADER)
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#---------------------------------------------------------------------------
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# Actual Source and Library control
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MAL_KERN_OBJECTS = \
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Malone_Firmware/DecKLib/KernelIF/DecKernelLib.o \
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Malone_Firmware/DecKLib/KernelIF/DecKernelLibPrivate.o \
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Malone_Firmware/DecKLib/Control/DecKernelLibHWControl.o \
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Malone_Firmware/DecKLib/Control/DecKernelLibHWIsr.o
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MAL_KERN_OBJECTS += Malone_Firmware/PAL/pal.o
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#---------------------------------------------------------------------------
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# Build flags
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DEFINES = -D DTV_GATHER_PERF_METRICS \
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-D MVD_DTV_USERDATA \
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-D MVD_WAIT_BOB_INACTIVE \
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-D DECLIB_FORCE_HW_STOP \
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-D MVD_NO_BSDMA_SAFETY_MARGIN \
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-D MVD_CQ_ENABLE_REFILL \
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-D MVD_SPP_HW_GOULOMB \
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-D SVC_SFA_ADD_ERROR_CHECKING \
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-D MVC_SFA_ADD_ERROR_CHECKING \
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-D SVC_SPP_SAVE_CTX_PER_VCL_NAL \
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-D MVD_CQ_CQSR \
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-D AVC_SUPPORT_THRU_MVC \
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-D MVC_ERROR_CONTROL_INSERT_SKIP_START_CONTROLS \
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-D DECLIB_CTX_FLUSH_AFTER_SAVE \
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-D DECLIB_SERVICE_EOS \
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-D MVD_PERF_MEASURE \
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-D VC1_ENABLED \
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-D HEVC_ENABLED \
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-D HEVC_CM_WORKAROUND \
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-D HEVC_NEW_OUTPUT_TRIGGER \
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-D HEVC_ALL_PICS_REF \
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-D HEVC_SCAL_LIST_USE_YCRCB_XREF \
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-D HEVC_SFA_ADD_ERROR_CHECKING \
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-D MVD_DFE_DBG \
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-D HEVC_JVT_MODEL=100 \
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-D PAL_CLOCK_API \
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-D SVC_ADDITIONAL_DEBUG \
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-D DIAG_SUPPORT_ENABLED \
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-D ENABLE_PERF_TIMER \
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-D FW_API_VERSION=19 \
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-D GLOBAL_USE_RUN_TIME_CFG \
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-D ENABLE_TRACE_IN_RELEASE=0 \
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-D YES=1 \
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-D NO=0 \
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-D NONE=0 \
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-D NUP=1 \
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-D UCOS=2 \
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-D UCOS3=3 \
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-D RTOS=0 \
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-D USE_DECODER \
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-D ARM=0 \
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-D MIPS=1 \
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-D X86=2 \
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-D OR1K=3 \
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-D CPU=0 \
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-D NO_AL=0 \
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-D CNXT_KAL=1 \
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-D NXP_OSAL=2 \
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-D OSAL=0 \
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-D ARM926=0 \
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-D ARMR5=1 \
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-D ARMA53=2 \
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-D ARM_CPU_TYPE=2 \
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-D ADS=0 \
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-D RVDS=1 \
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-D GNU_MIPS=2 \
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-D GNU_MIPS_LNX=3 \
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-D GNU_ARM=4 \
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-D GNU_ARM_SOURCERY=5 \
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-D GNU_X86=6 \
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-D WIN_X86=7 \
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-D DS5=8 \
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-D GNU_OR32=9 \
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-D GNU_ARM_LINARO=10 \
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-D GNU_OR1K=11 \
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-D TOOLSET=10 \
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-D NO_DEBUG=0 \
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-D BUILD_DEBUG=1 \
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-D ARRAY_DEBUG=2 \
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-D FULL_DEBUG=3 \
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-D DEBUG_CAPS=0 \
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-D GENTB_PLATFORM=0 \
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-D WIN_LIB=1 \
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-D GEN_TB_ENC=2 \
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-D TARGET_PLATFORM=0 \
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-D VIDEO_TRANS=0 \
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-D GTB_TRANS=1 \
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-D GTB_DEC=2 \
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-D WINDSOR_LIB=3 \
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-D GTB_ENC=4 \
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-D MEDIA_DEC=5 \
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-D MEDIA_LIB=6 \
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-D VPU_TEST_APP=7 \
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-D TARGET_APP=7 \
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-D PAL_CLOCK_API \
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-D SVC_ADDITIONAL_DEBUG \
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-D DIAG_SUPPORT_ENABLED \
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-D ENABLE_PERF_TIMER \
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-D FW_API_VERSION=19 \
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-D GLOBAL_USE_RUN_TIME_CFG \
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-D DISABLE_TRACE \
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-D ENABLE_TRACE_IN_RELEASE=0 \
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-D YES=1 \
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-D NO=0 \
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-D NONE=0 \
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-D NUP=1 \
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-D UCOS=2 \
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-D UCOS3=3 \
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-D RTOS=0 \
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-D USE_DECODER \
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-D CHIP=0 \
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-D EMULATION=1 \
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-D HAPS=2 \
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-D SIMULATION=3 \
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-D CMODEL=4 \
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-D TARGET_LEVEL=0 \
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-D SVC_DISABLED=0 \
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-D SVC_ENABLED=1 \
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-D SVC_SUPPORT=0 \
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-D MVC_DISABLED=0 \
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-D MVC_ENABLED=1 \
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-D MVC_SUPPORT=1 \
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-D SFA_DISABLED=0 \
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-D SFA_ENABLED=1 \
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-D SFA_SUPPORT=1 \
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-D CNXT_HW=0 \
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-D NXP_HW=1 \
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-D HWLIB=1 \
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-D DTV=0 \
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-D STB=1 \
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-D PLAYMODE=0 \
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-D STANDARD=0 \
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-D REBOOT=1 \
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-D BOOT_ARCH=0 \
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-D TBPLAYER_FLOW_CHANGE_ON_REF_FRMS \
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-D PULSAR_MERGE \
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-D FSLCACHE_ENABLED \
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-D DECLIB_ENABLE_DFE -D DECLIB_ENABLE_DBE \
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-D DECLIB_ENABLE_DCP -D MVD_DCP_DYNAMIC_CONFIG \
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-D DECLIB_4K_SUPPORTED -D HEVC_LEVEL_5PT0_SUPPORT \
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-D PLAYER_LOCAL_THREAD \
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-D DECLIB_ISR_IN_THREAD_CTX \
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-D JPG_ENABLED \
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-D JPGD_AUTO_DOWN_SCALE \
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-D SPARK_ENABLED \
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-D RV_ENABLED \
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-D VP6_ENABLED \
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-D VP8_ENABLED \
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-D JPG_DPV_ENABLED \
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-D MALONE_64BIT_ADDR \
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-D DISABLE_TRACE
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MALONE_KERN_DEFINEFLAGS = $(DEFINES)
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MALONE_KERN_DEFINEFLAGS += -D VPU_KERNEL_BUILD
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EXTRA_CFLAGS += $(MALONE_KERN_DEFINEFLAGS)
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EXTRA_CFLAGS += $(MALONE_KERN_HEADER)
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ifeq ($(CONFIG_MXC_VPU_MALONE_DEBUG),y)
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EXTRA_CFLAGS += -DDEBUG
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endif
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obj-$(CONFIG_MXC_VPU_MALONE) = decoder.o
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decoder-objs = mxc_vpu-malone.o \
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$(MAL_KERN_OBJECTS)
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cmd_files := $(foreach f,$(decoder-objs),$(dir $(f)).$(notdir $(f)).cmd)
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clean:
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rm -rf $(decoder-objs) $(cmd_files) *.o .*.cmd modules.builtin modules.order
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@ -0,0 +1,326 @@
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/***************************************************
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Copyright (c) 2015 Amphion Semiconductor Ltd
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All rights reserved.
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***************************************************
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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****************************************************
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Author : Media IP FW team ( Belfast and Shanghai )
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File name : DecLibHWControl.c
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Notes : Processes commands from decoder lib scheduler
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Establishes context for and makes calls to
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the base decoders
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This file provides the hardware facing aspect to
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the interface. It is part of a group with
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DecLibStreamControl.c which provides the
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HW funtionality
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******************************************************/
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/////////////////////////////////////////////////////////////////////////////////
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// Header Files
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/////////////////////////////////////////////////////////////////////////////////
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#include "basetype.h"
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#include "mediaip_fw_types.h"
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#include "pal.h"
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#include "mvd_types.h"
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#include "mvd_reg_map.h"
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#include "mvd_sif_control.h"
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#include "DecKernelLibPrivate.h"
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#include "DecKernelLibHWControl.h"
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/////////////////////////////////////////////////////////////////////////////////
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// Extern Function Prototypes
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/////////////////////////////////////////////////////////////////////////////////
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extern MEDIAIP_IRQ_RETCODE mvd_kernel_hw_primary_isr ( u_int32 irq_val );
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extern MEDIAIP_IRQ_RETCODE mvd_kernel_hw_secondary_isr ( u_int32 irq_val );
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/////////////////////////////////////////////////////////////////////////////////
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// Private Function Prototypes
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/////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////
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// Global Variables
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/////////////////////////////////////////////////////////////////////////////////;
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extern DEC_KERNEL_LIB gDecKernelLib;
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MALONE_KERNEL_HW_SESSION gMvdKernelHw[(DECODERLIB_MAX_MALONES + 1)];
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pMALONE_KERNEL_HW_SESSION pgMVDKernelHw;
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u_int32 gMaloneList[(DECODERLIB_MAX_MALONES + 1)] = { MALONE_HW_1,
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#if DECODERLIB_MAX_MALONES > 1
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MALONE_HW_2,
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#endif
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MALONE_SW };
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static u_int32 uSWMaloneRegSpace[2048]; /* Until we are sure we have eliminated register access */
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/* for functions using the 'SW Malone', point them here */
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extern u_int32 uDecLibIrqPin[DECODERLIB_MAX_MALONES][0x2];
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/////////////////////////////////////////////////////////////////////////////////
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// Code
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/////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////
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// FUNCTION: mvd_kernel_hw_control_init //
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// //
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// DESCRIPTION: Perform all HW initialisation and shared structure setup //
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// //
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// INPUTS: uMaloneID - The ID of the Malone for which the info is to //
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// be restored //
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// pCtxArea - Pointer to area of memory from which data is to be //
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// read //
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// //
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// OUTPUTS: None. //
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// //
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// RETURNS: None. //
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// //
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// NOTES: None. //
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// //
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// CONTEXT: This function must be called from non-interrupt context //
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// //
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////////////////////////////////////////////////////////////////////////////////////
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void mvd_kernel_hw_control_init ( DECODERLIB_KERNEL_CFG * pCfg )
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{
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/* Init the handles */
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/* This sets up the reg pointers so do it first */
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mvd_kernel_hw_init_handles ( pCfg,
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TRUE );
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/* Default global pointers to a 1st Malone focus */
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mvd_kernel_hw_set_focus ( MALONE_HW_1, &pgMVDKernelHw );
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}
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////////////////////////////////////////////////////////////////////////////////////
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// FUNCTION: mvd_kernel_hw_set_malone_instance //
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// //
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// DESCRIPTION: Look for the most appropriate Malone instance to service //
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// the command for a specified stream //
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// //
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// INPUTS: uStrId - The Stream ID //
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// bSWCmd - is the command to be carried out for this stream //
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// capable of being handled without using the HW engine? //
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// uHWIndex - HW Index suggested by scheduler //
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// bUseSch - Set to guarantee scheduler suggested unit is used //
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// //
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// OUTPUTS: None. //
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// //
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// RETURNS: The most suitable Malone ID to be used //
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// //
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// NOTES: This function must return a value. //
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// //
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// CONTEXT: This function must be called from non-interrupt context //
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// //
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////////////////////////////////////////////////////////////////////////////////////
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u_int32 mvd_kernel_hw_set_malone_instance ( u_int32 uStrId,
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bool bSWCmd,
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u_int32 uHWIndex,
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bool bUseSch
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)
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{
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u_int32 uIdx = 0;
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if ( bUseSch )
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{
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return uHWIndex;
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}
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for ( uIdx = 0; uIdx < gDecKernelLib.uNumMalones; uIdx++ )
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{
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/* Even if there is no command active, this is a valid check as */
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/* it avoids need for a context change if it matches */
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if ( gMvdKernelHw[uIdx].uStrID == uStrId )
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{
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return uIdx;
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}
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}
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if ( bSWCmd ) return MALONE_SW;
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/* Look for free Malone - this function should not be called */
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/* unless this is a SW command or there is a free Malone */
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for ( uIdx = 0; uIdx < gDecKernelLib.uNumMalones; uIdx++ )
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{
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/* Even if there is no command active, this is a valid check as */
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/* it avoids need for a context change if it matches */
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if ( gMvdKernelHw[uIdx].eState == MALONE_INACTIVE )
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{
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break;
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}
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}
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/* Do not assign this stream and do NOT make it active yet */
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/* Only make this malone active when the command is issued */
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/* This is necessary so we we can trigger context switches */
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/* We should set the global pointer though so calls to sif */
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/* etc can get correct functions!! */
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mvd_kernel_hw_set_focus ( uIdx, &pgMVDKernelHw );
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return uIdx;
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}
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////////////////////////////////////////////////////////////////////////////////////
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// FUNCTION: mvd_kernel_hw_set_focus //
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// //
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// DESCRIPTION: Changes focus to the selected Malone HW unit //
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// //
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// INPUTS: uMaloneID - The ID of the Malone //
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// //
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// OUTPUTS: ppMVDHw - Pointer to a HW session structure for the specified //
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// Malone //
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// //
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// RETURNS: None. //
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// //
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// NOTES: Only makes sense in multi-malone configs //
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// //
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// CONTEXT: This function may be called from any context //
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// //
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////////////////////////////////////////////////////////////////////////////////////
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void mvd_kernel_hw_set_focus ( u_int32 uMaloneID, pMALONE_KERNEL_HW_SESSION * ppMVDHw )
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{
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*ppMVDHw = ( MALONE_KERNEL_HW_SESSION * )&gMvdKernelHw[uMaloneID];
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}
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////////////////////////////////////////////////////////////////////////////////////
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// FUNCTION: mvd_kernel_hw_init_handles //
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// //
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// DESCRIPTION: Initialise the HW session handles //
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// //
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// INPUTS: pCfg - A pointer to the DecLib Config structure //
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// bSoftInit - If set, the FW pointers get established - leave //
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// FALSE when restarting from a snapshot //
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// //
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// OUTPUTS: None. //
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// //
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// RETURNS: None. //
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// //
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// NOTES: None. //
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// //
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// CONTEXT: This function must be called from non-interrupt context //
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// //
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////////////////////////////////////////////////////////////////////////////////////
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void mvd_kernel_hw_init_handles ( DECODERLIB_KERNEL_CFG * pCfg,
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bool bSoftInit
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)
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{
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u_int32 uIdx;
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pMALONE_KERNEL_HW_SESSION pMVDHw;
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MvdHwRegMap *pMvdReg;
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for ( uIdx = 0; uIdx < (gDecKernelLib.uNumMalones + 1); uIdx++ )
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{
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/* If we have set up all the HW handles then move to the SW */
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/* handle and set it up */
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if ( uIdx == gDecKernelLib.uNumMalones ) uIdx = DECODERLIB_MAX_MALONES;
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pMVDHw = &gMvdKernelHw[uIdx];
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if ( bSoftInit )
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{
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pMVDHw->eState = MALONE_INACTIVE;
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pMVDHw->uStrID = 0;
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pMVDHw->uForceFIQ = 0;
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pMVDHw->uForceDFEFIQ = 0;
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|
||||
/* Malone ID that the instance uses, normally fixed... */
|
||||
pMVDHw->uMaloneID = gMaloneList[uIdx];
|
||||
}
|
||||
|
||||
if ( pMVDHw->uMaloneID == DECODERLIB_MAX_MALONES )
|
||||
{
|
||||
pMvdReg = ( MvdHwRegMap * )uSWMaloneRegSpace;
|
||||
}
|
||||
else if ( pMVDHw->uMaloneID == MALONE_HW_2 )
|
||||
{
|
||||
pMvdReg = ( MvdHwRegMap * ) ( pCfg->uMaloneBaseAddr[0x1] + pCfg->uMaloneHifOffset[0x1] );
|
||||
}
|
||||
else
|
||||
{
|
||||
pMvdReg = ( MvdHwRegMap * ) ( pCfg->uMaloneBaseAddr[0x0] + pCfg->uMaloneHifOffset[0x0] );
|
||||
}
|
||||
|
||||
if ( pMVDHw->uMaloneID == MALONE_SW )
|
||||
{
|
||||
pMVDHw->msd_regp = ( MvdHwRegMap * )pMvdReg;
|
||||
pMVDHw->hif_regp = ( MvdHwRegHifMap * )pMvdReg;
|
||||
pMVDHw->sif_regp = ( MvdHwRegSifMap * )pMvdReg;
|
||||
pMVDHw->ctx_regp = ( MvdHwRegCtxMap * )pMvdReg;
|
||||
pMVDHw->rsb_regp = ( MvdHwReg * )pMvdReg;
|
||||
pMVDHw->rpr_regp = ( MvdHwRegRprMap * )pMvdReg;
|
||||
pMVDHw->spp_regp = ( MvdHwRegSppMap * )pMvdReg;
|
||||
pMVDHw->avc_regp = ( MvdHwRegH264Map * )pMvdReg;
|
||||
pMVDHw->mp2d_regp = ( MvdHwRegMp2dMap * )pMvdReg;
|
||||
pMVDHw->avsd_regp = ( MvdHwRegAvsdMap * )pMvdReg;
|
||||
pMVDHw->aspd_regp = ( MvdHwRegAspdMap * )pMvdReg;
|
||||
pMVDHw->vc1d_regp = ( MvdHwRegVc1dMap * )pMvdReg;
|
||||
pMVDHw->jpgd_regp = ( MvdHwRegAspdMap * )pMvdReg;
|
||||
pMVDHw->rvid_regp = ( MvdHwRegRvidMap * )pMvdReg;
|
||||
pMVDHw->hevc_regp = ( MvdHwRegHevcMap * )pMvdReg;
|
||||
pMVDHw->on2d_regp = ( MvdHwRegOn2dMap * )pMvdReg;
|
||||
pMVDHw->cq_regp = ( MvdHwRegCqMap * )pMvdReg;
|
||||
pMVDHw->rc4_regp = ( MvdHwRegRC4Map * )pMvdReg;
|
||||
pMVDHw->dfe_regp = ( MvdHwRegDfeMap * )pMvdReg;
|
||||
pMVDHw->dbe_regp[0x0] = ( MvdHwRegDbeMap * )pMvdReg;
|
||||
pMVDHw->dbe_regp[0x1] = ( MvdHwRegDbeMap * )pMvdReg;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
pMVDHw->msd_regp = pMvdReg;
|
||||
pMVDHw->hif_regp = &( pMvdReg->HifMap.hif_map );
|
||||
pMVDHw->sif_regp = &( pMvdReg->SifMap.sif_map );
|
||||
pMVDHw->ctx_regp = &( pMvdReg->CtxMap.ctx_map );
|
||||
pMVDHw->rpr_regp = &( pMvdReg->RprMap.rpr_map );
|
||||
pMVDHw->spp_regp = &( pMvdReg->SppMap.spp_map );
|
||||
pMVDHw->avc_regp = &( pMvdReg->DecMap.h264_map );
|
||||
pMVDHw->mp2d_regp = &( pMvdReg->DecMap.mp2d_map );
|
||||
pMVDHw->aspd_regp = &( pMvdReg->DecMap.aspd_map );
|
||||
pMVDHw->avsd_regp = &( pMvdReg->DecMap.avsd_map );
|
||||
pMVDHw->vc1d_regp = &( pMvdReg->DecMap.vc1d_map );
|
||||
pMVDHw->jpgd_regp = &( pMvdReg->DecMap.aspd_map );
|
||||
pMVDHw->on2d_regp = &( pMvdReg->DecMap.on2d_map );
|
||||
pMVDHw->rvid_regp = &( pMvdReg->DecMap.rvid_map );
|
||||
pMVDHw->hevc_regp = &( pMvdReg->DecMap.hevc_map );
|
||||
pMVDHw->bbd_regp = &( pMvdReg->BbdMap.bbd_map );
|
||||
pMVDHw->cq_regp = &( pMvdReg->CqMap.cq_map );
|
||||
pMVDHw->rc4_regp = &( pMvdReg->RC4Map.RC4_map );
|
||||
pMVDHw->dfe_regp = &( pMvdReg->DcpMap.dfe_map );
|
||||
pMVDHw->dbe_regp[0x0] = &( pMvdReg->DcpMap.dbe_map[0x0] );
|
||||
pMVDHw->dbe_regp[0x1] = &( pMvdReg->DcpMap.dbe_map[0x1] );
|
||||
|
||||
if ( pMVDHw->uMaloneID == MALONE_HW_2 )
|
||||
{
|
||||
pMVDHw->rsb_regp = ( MvdHwReg * ) pCfg->uMaloneBaseAddr[0x1] ;
|
||||
}
|
||||
else
|
||||
{
|
||||
pMVDHw->rsb_regp = ( MvdHwReg * ) pCfg->uMaloneBaseAddr[0x0] ;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Filename: DecLibHWControl.h
|
||||
Description:
|
||||
|
||||
**************************************************/
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _DECODER_LIB_HW_CONTROL_H_
|
||||
#define _DECODER_LIB_HW_CONTROL_H_
|
||||
|
||||
#include "mvd_types.h"
|
||||
#include "mvd_reg_map.h"
|
||||
#include "DecKernelLib.h"
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Macros
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define MALONE_HW_1 0 /* Identifiers for the Malone units */
|
||||
#define MALONE_HW_2 1
|
||||
#define MALONE_SW DECODERLIB_MAX_MALONES /* Sw Malone does not exist! Simply a */
|
||||
/* control structure for carrying out */
|
||||
/* commands which do not need a HW unit */
|
||||
#define MALONE_SW_IRQ 0xdeaf
|
||||
|
||||
#define DECODERLIB_ISR_QU_SIZE ( DECODERLIB_MAX_MALONES * 4 )
|
||||
#define DECODERLIB_SECONDARY_ISR_EVENT 0x80000000
|
||||
#define DECODERLIB_EVENT_MASK 0x7FFFFFFF
|
||||
|
||||
#define DECODERLIB_FORCEIRQ_BIT_SET( uVal ) (( uVal & 0x1 ) << 30 )
|
||||
#define DECODERLIB_FORCEIRQ_BIT_GET( uVal ) (( uVal >> 30 ) & 0x1 )
|
||||
#define DECODERLIB_FORCEDFEIRQ_BIT_SET( uVal ) (( uVal & 0x1 ) << 29 )
|
||||
#define DECODERLIB_FORCEDFEIRQ_BIT_GET( uVal ) (( uVal >> 29 ) & 0x1 )
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Types
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Decoder Library HW State
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MALONE_INACTIVE = 0,
|
||||
MALONE_ACTIVE,
|
||||
MALONE_BE_ACTIVE
|
||||
|
||||
} MALONE_STATE;
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Decoder Library HW Control Context Info
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
MALONE_STATE eState;
|
||||
u_int32 uStrID;
|
||||
|
||||
u_int32 uForceFIQ;
|
||||
u_int32 uForceDFEFIQ;
|
||||
u_int32 uChipVer; /* Hold "malone" version to be filled in from Malone HW register */
|
||||
u_int32 uChipMnrVer; /* Hold "malone" minor version to be filled in from Malone HW register */
|
||||
u_int32 uChipSubVer; /* Hold metal version to be filled in by higher level control */
|
||||
u_int32 uHWFeatures;
|
||||
u_int32 uForceCacheFlush; /* Cache reset issue workaround purpose for Kronos and Fusion RevA */
|
||||
u_int32 bPreparser; /* Set TRUE to indicate a preparser is in place */
|
||||
u_int32 bCQ; /* Set TRUE to indicate a command queue is in place */
|
||||
u_int32 bDCP; /* Set TRUE to indicate unit can operate in decoupled mode */
|
||||
u_int32 uNumDBEs; /* Indicates the number of decoupled back ends available */
|
||||
u_int32 bFBC; /* Set TRUE to indicate Frame buffer Compression support */
|
||||
u_int32 uRSBSize;
|
||||
u_int32 uMaloneID;
|
||||
u_int32 bPixIf;
|
||||
u_int32 bXBUS;
|
||||
|
||||
u_int32 uCQProcType[DECODERLIB_MAX_CQ_PER_MALONE]; /* Specifies what type of processing each of the CQ units is doing */
|
||||
|
||||
MALONE_STATE eDFEState; /* If the front end of the HW is active in isolation - specifies state */
|
||||
u_int8 usDFEStrID; /* If the front end of the HW is active in isolation - specifies */
|
||||
/* which stream is assigned */
|
||||
|
||||
u_int32 uDmaMemSize;
|
||||
void * pDmaMemArea;
|
||||
|
||||
MvdHwRegMap * msd_regp;
|
||||
MvdHwRegHifMap * hif_regp;
|
||||
MvdHwRegSifMap * sif_regp;
|
||||
MvdHwRegCtxMap * ctx_regp;
|
||||
MvdHwReg * rsb_regp;
|
||||
MvdHwRegRprMap * rpr_regp;
|
||||
MvdHwRegSppMap * spp_regp;
|
||||
MvdHwRegH264Map * avc_regp;
|
||||
MvdHwRegMp2dMap * mp2d_regp;
|
||||
MvdHwRegAvsdMap * avsd_regp;
|
||||
MvdHwRegAspdMap * aspd_regp;
|
||||
MvdHwRegVc1dMap * vc1d_regp;
|
||||
MvdHwRegAspdMap * jpgd_regp;
|
||||
MvdHwRegOn2dMap * on2d_regp;
|
||||
MvdHwRegRvidMap * rvid_regp;
|
||||
MvdHwRegHevcMap * hevc_regp;
|
||||
MvdHwRegBbdMap * bbd_regp;
|
||||
MvdHwRegDbgMap * dbg_regp;
|
||||
MvdHwRegCqMap * cq_regp;
|
||||
MvdHwRegRC4Map * rc4_regp;
|
||||
MvdHwRegDfeMap * dfe_regp;
|
||||
MvdHwRegDbeMap * dbe_regp[DECODERLIB_MAX_DBE_UNITS];
|
||||
|
||||
} MALONE_KERNEL_HW_SESSION, *pMALONE_KERNEL_HW_SESSION;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Function definitions
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
void mvd_kernel_hw_control_init ( DECODERLIB_KERNEL_CFG * pCfg );
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: mvd_kernel_hw_set_focus //
|
||||
// //
|
||||
// DESCRIPTION: Changes focus to the selected Malone HW unit //
|
||||
// //
|
||||
// INPUTS: uMaloneID - The ID of the Malone //
|
||||
// //
|
||||
// OUTPUTS: ppMVDHw - Pointer to a HW session structure for the specified //
|
||||
// Malone //
|
||||
// //
|
||||
// RETURNS: None. //
|
||||
// //
|
||||
// NOTES: Only makes sense in multi-malone configs //
|
||||
// //
|
||||
// CONTEXT: This function may be called from any context //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void mvd_kernel_hw_set_focus ( u_int32 uMaloneID, pMALONE_KERNEL_HW_SESSION * ppMVDHw );
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: mvd_kernel_hw_init_handles //
|
||||
// //
|
||||
// DESCRIPTION: Initialise the HW session handles //
|
||||
// //
|
||||
// INPUTS: pCfg - A pointer to the DecLib Config structure //
|
||||
// bSoftInit - If set, the FW pointers get established - leave //
|
||||
// FALSE when restarting from a snapshot //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: None. //
|
||||
// //
|
||||
// NOTES: None. //
|
||||
// //
|
||||
// CONTEXT: This function must be called from non-interrupt context //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void mvd_kernel_hw_init_handles ( DECODERLIB_KERNEL_CFG * pCfg,
|
||||
bool bSoftInit );
|
||||
|
||||
#endif /* _DECODER_LIB_HW_CONTROL_H_ */
|
||||
|
||||
/* End of file */
|
||||
|
|
@ -0,0 +1,467 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
File name : DecLibHWIsr.c
|
||||
Notes : Provides the HW Interrupt Service Routines
|
||||
|
||||
*******************************************************/
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header Files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "basetype.h"
|
||||
#include "mediaip_fw_types.h"
|
||||
#include "pal.h"
|
||||
|
||||
#include "mvd.h"
|
||||
#include "mvd_types.h"
|
||||
#include "mvd_reg_map.h"
|
||||
#include "mvd_sif_control.h"
|
||||
|
||||
#include "DecKernelLibHWControl.h"
|
||||
#include "DecKernelLibPrivate.h"
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Variables
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
extern pMALONE_KERNEL_HW_SESSION pgMVDKernelHw;
|
||||
extern u_int32 uMvdKernelIrqPin[DECODERLIB_MAX_MALONES][0x2];
|
||||
extern DEC_KERNEL_LIB gDecKernelLib;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Macros
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Private Prototypes
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void mvd_kernel_hw_isr_event ( u_int32 uMaloneIdx,
|
||||
u_int32 * puIrqStatus );
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Extern Prototypes
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Code
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: mvd_hw_sesh_isr //
|
||||
// //
|
||||
// DESCRIPTION: Malone HW ISR //
|
||||
// //
|
||||
// INPUTS: irq_val - Identification Parameter from which source of call //
|
||||
// may be ascertained //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: MEDIAIP_IRQ_RETCODE //
|
||||
// //
|
||||
// NOTES: None. //
|
||||
// //
|
||||
// CONTEXT: This function may be called from any context //
|
||||
// Since it is an isr, that may be strange but it can be called to //
|
||||
// handle SW commands in thread context only //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define CTX_DBG(x)
|
||||
|
||||
MEDIAIP_IRQ_RETCODE mvd_kernel_hw_primary_isr ( u_int32 irq_val )
|
||||
{
|
||||
u_int32 sif_irq_status[0x3] = { 0x0 };
|
||||
u_int32 uActMaloneID, uData;
|
||||
#if ( TARGET_APP == GTB_DEC ) || ( TARGET_APP == MEDIA_DEC ) || ( TARGET_APP == VIDEO_TRANS ) || ( TARGET_APP == GTB_TRANS )
|
||||
u_int32 uIrqTarget0, uIrqTarget1;
|
||||
#endif
|
||||
u_int32 uForceFIQ = 0, uForceDFEFIQ = 0;
|
||||
|
||||
/* Future Proof... */
|
||||
/* If we have two levels of interrupt or we process interrupts in thread context */
|
||||
/* we need to save and restore HW focus */
|
||||
pMALONE_KERNEL_HW_SESSION pLocMVDHw = pgMVDKernelHw;
|
||||
|
||||
/* Work out which Malone instance caused this isr and set HW focus accordingly */
|
||||
|
||||
#if ( TARGET_APP == GTB_DEC ) || ( TARGET_APP == MEDIA_DEC ) || ( TARGET_APP == VIDEO_TRANS ) || ( TARGET_APP == GTB_TRANS )
|
||||
|
||||
pal_int_get_irq_line ( uMvdKernelIrqPin[0x0][0x0],
|
||||
&uIrqTarget0
|
||||
);
|
||||
pal_int_get_irq_line ( uMvdKernelIrqPin[0x0][0x1],
|
||||
&uIrqTarget1
|
||||
);
|
||||
|
||||
uActMaloneID = ( irq_val == MALONE_SW_IRQ ) ? MALONE_SW :
|
||||
(( irq_val == uIrqTarget0 ) | ( irq_val == uIrqTarget1 )) ? MALONE_HW_1 :
|
||||
MALONE_HW_2;
|
||||
|
||||
#else
|
||||
|
||||
uActMaloneID = ( irq_val == MALONE_SW_IRQ ) ? MALONE_SW :
|
||||
(( irq_val == uMvdKernelIrqPin[0x0][0x0] ) | ( irq_val == uMvdKernelIrqPin[0x0][0x1] )) ? MALONE_HW_1 :
|
||||
MALONE_HW_2;
|
||||
|
||||
#endif
|
||||
|
||||
mvd_kernel_hw_set_focus ( uActMaloneID, &pgMVDKernelHw );
|
||||
|
||||
MVD_REG_READ( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->msd_data0_reg, uData );
|
||||
|
||||
MVD_REG_WRITE( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->msd_data0_reg, 0 );
|
||||
|
||||
uForceFIQ = ( uData & 0x1 ) ? 1 : 0;
|
||||
uForceDFEFIQ = ( uData & 0x2 ) ? 1 : 0;
|
||||
|
||||
if ( uActMaloneID != MALONE_SW )
|
||||
{
|
||||
u_int32 uClearVal;
|
||||
|
||||
/* Break down sif IRQ sources */
|
||||
MVD_REG_READ( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->intr_status, sif_irq_status[0x0] );
|
||||
MVD_REG_READ( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->intr2_status, sif_irq_status[0x1] );
|
||||
MVD_REG_READ( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->intr3_status, sif_irq_status[0x2] );
|
||||
|
||||
pal_trace( DECODER_TL_INFO, "mvd_kernel_hw_primary_isr(%d): opening sif_irq_status = 0x%x\n", irq_val, sif_irq_status[0x0]);
|
||||
pal_trace( DECODER_TL_INFO, "mvd_kernel_hw_primary_isr(%d): opening sif_irq_status[0x1] = 0x%x\n", irq_val, sif_irq_status[0x1]);
|
||||
pal_trace( DECODER_TL_INFO, "mvd_kernel_hw_primary_isr(%d): opening sif_irq_status[0x2] = 0x%x\n", irq_val, sif_irq_status[0x2]);
|
||||
|
||||
/* Clear the interrupt bits we're going to handle here */
|
||||
|
||||
#ifdef FW_PES_PARSE_AS_FIQ
|
||||
|
||||
uClearVal = sif_irq_status[0x0] & ( MSD_SIF_INTR_BSDMA_BIT |
|
||||
MSD_SIF_INTR_FORCE_EXIT_BIT |
|
||||
MSD_SIF_INTR_DISPQ_PULL_BIT |
|
||||
MSD_SIF_INTR_SEMAPHORE_BIT |
|
||||
MSD_SIF_INTR_IMAGE_DONE_BIT |
|
||||
MSD_SIF_INTR_SLICE_DONE_BIT |
|
||||
MSD_SIF_INTR_FORCE_ENTRY_BIT
|
||||
);
|
||||
|
||||
MVD_REG_WRITE( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->intr_status, uClearVal );
|
||||
|
||||
#else
|
||||
|
||||
uClearVal = sif_irq_status[0x0] & ( MSD_SIF_INTR_BSDMA_BIT |
|
||||
MSD_SIF_INTR_PES_BIT |
|
||||
MSD_SIF_INTR_SCODE_FOUND_BIT |
|
||||
MSD_SIF_INTR_DISPQ_PULL_BIT |
|
||||
MSD_SIF_INTR_SEMAPHORE_BIT |
|
||||
MSD_SIF_INTR_IMAGE_DONE_BIT |
|
||||
MSD_SIF_INTR_SLICE_DONE_BIT |
|
||||
MSD_SIF_INTR_FORCE_ENTRY_BIT
|
||||
);
|
||||
|
||||
MVD_REG_WRITE( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->intr_status, uClearVal );
|
||||
|
||||
#endif /* FW_PES_PARSE_AS_FIQ */
|
||||
|
||||
/* Read it back to ensure write has made it to Malone */
|
||||
MVD_REG_READ( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->intr_status, uClearVal );
|
||||
|
||||
/* Also re-clear the INTC bit which brought us in here since */
|
||||
/* it will have been reset. */
|
||||
pal_int_clear ( irq_val,
|
||||
TRUE
|
||||
);
|
||||
|
||||
#ifdef FW_PARSE_PES
|
||||
#ifdef FW_PES_PARSE_AS_FIQ
|
||||
|
||||
/* Pes FW handling done at higher level */
|
||||
/* Re-maps the force-exit ISR as the startcode */
|
||||
|
||||
/* TODO-KMC */
|
||||
/* Does this mean a normal engine startcode is mapped as a force-exit? I guess it does */
|
||||
/* So if we were parsing PES as an FIQ we would not actually be in this function if it */
|
||||
/* were a PES startcode and so the below event must be a normal startcode? */
|
||||
|
||||
if ( sif_irq_status[0x0] & MSD_SIF_INTR_FORCE_EXIT_BIT )
|
||||
{
|
||||
sif_irq_status[0x0] |= MSD_SIF_INTR_SCODE_FOUND_BIT;
|
||||
}
|
||||
#else
|
||||
/* PES isr */
|
||||
if ( sif_irq_status[0x0] & MSD_SIF_INTR_SCODE_FOUND_BIT )
|
||||
{
|
||||
u_int32 scode_status;
|
||||
|
||||
MVD_REG_READ( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->bs2rbsp_status, scode_status );
|
||||
|
||||
if ( scode_status & MSD_SIF_BS2RBSP_GOT_PESSCODE )
|
||||
{
|
||||
sesh_pes_isr ( irq_val );
|
||||
}
|
||||
|
||||
/* If it was just a PES startcode, then don't tell the engine */
|
||||
/* that there was a startcode, as will get handled later */
|
||||
if (( scode_status & MSD_SIF_BS2RBSP_GOT_SCODE ) == 0 )
|
||||
{
|
||||
sif_irq_status[0x0] &= ~(MSD_SIF_INTR_SCODE_FOUND_BIT);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if ( sif_irq_status[0x1] & ( MSD_SIF_INTR2_CSC_BIT ) )
|
||||
{
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr2_status, sif_irq_status[0x1] & ( MSD_SIF_INTR2_CSC_BIT ) );
|
||||
}
|
||||
|
||||
if ( sif_irq_status[0x1] & ( MSD_SIF_INTR2_CQ_BIT ) )
|
||||
{
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr2_status, sif_irq_status[0x1] & ( MSD_SIF_INTR2_CQ_BIT ) );
|
||||
}
|
||||
|
||||
if ( sif_irq_status[0x1] & ( MSD_SIF_INTR2_DFE_DONE_BIT ) )
|
||||
{
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr2_status, sif_irq_status[0x1] & ( MSD_SIF_INTR2_DFE_DONE_BIT ) );
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr2_status, sif_irq_status[0x1] & ( MSD_SIF_INTR2_DFE_SLC_DONE_BIT ) );
|
||||
}
|
||||
|
||||
if ( sif_irq_status[0x1] & MSD_SIF_INTR2_DFE_SLC_DONE_BIT )
|
||||
{
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr2_status, sif_irq_status[0x1] & ( MSD_SIF_INTR2_DFE_SLC_DONE_BIT ) );
|
||||
}
|
||||
|
||||
if ( sif_irq_status[0x2] & MSD_SIF_INTR3_DBE0_CQ_BIT )
|
||||
{
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr3_status, sif_irq_status[0x2] & ( MSD_SIF_INTR3_DBE0_CQ_BIT ) );
|
||||
}
|
||||
|
||||
if ( sif_irq_status[0x2] & MSD_SIF_INTR3_DBE1_CQ_BIT )
|
||||
{
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr3_status, sif_irq_status[0x2] & ( MSD_SIF_INTR3_DBE1_CQ_BIT ) );
|
||||
}
|
||||
|
||||
if ( sif_irq_status[0x2] &
|
||||
( MSD_SIF_INTR3_DBE0_DONE_BIT | MSD_SIF_INTR3_DBE1_DONE_BIT | MSD_SIF_INTR3_DBE0_SLC_DONE_BIT | MSD_SIF_INTR3_DBE1_SLC_DONE_BIT )
|
||||
)
|
||||
{
|
||||
u_int32 uMask = ( MSD_SIF_INTR3_DBE0_DONE_BIT |
|
||||
MSD_SIF_INTR3_DBE1_DONE_BIT |
|
||||
MSD_SIF_INTR3_DBE0_SLC_DONE_BIT |
|
||||
MSD_SIF_INTR3_DBE1_SLC_DONE_BIT
|
||||
);
|
||||
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr3_status, sif_irq_status[0x2] & uMask );
|
||||
}
|
||||
}
|
||||
else /* We wish to process a command without accessing HW */
|
||||
{
|
||||
sif_irq_status[0x0] = 0;
|
||||
}
|
||||
|
||||
pal_trace( DECODER_TL_DEBUG, "-> mvd_kernel_hw_primary_isr( ) : uForceFIQ = 0x%x\n", uForceFIQ );
|
||||
|
||||
/* Decode engine IRQs */
|
||||
if (( uActMaloneID == MALONE_SW ) ||
|
||||
( uForceFIQ ) ||
|
||||
( uForceDFEFIQ ) ||
|
||||
( sif_irq_status[0x0] & ( MSD_SIF_INTR_IMAGE_DONE_BIT | MSD_SIF_INTR_SLICE_DONE_BIT | MSD_SIF_INTR_SCODE_FOUND_BIT | MSD_SIF_INTR_FORCE_ENTRY_BIT | MSD_SIF_INTR_BSDMA_BIT )) ||
|
||||
( sif_irq_status[0x1] & ( MSD_SIF_INTR2_CSC_BIT | MSD_SIF_INTR2_DFE_DONE_BIT | MSD_SIF_INTR2_DFE_SLC_DONE_BIT | MSD_SIF_INTR2_CQ_BIT )) ||
|
||||
( sif_irq_status[0x2] & ( MSD_SIF_INTR3_DBE0_DONE_BIT | MSD_SIF_INTR3_DBE1_DONE_BIT | MSD_SIF_INTR3_DBE0_SLC_DONE_BIT | MSD_SIF_INTR3_DBE1_SLC_DONE_BIT | MSD_SIF_INTR3_DBE0_CQ_BIT | MSD_SIF_INTR3_DBE1_CQ_BIT ))
|
||||
)
|
||||
{
|
||||
pal_trace ( DECODER_TL_DEBUG,
|
||||
"-> mvd_kernel_hw_primary_isr( ) : sif_irq_status[0x0] = 0x%x : sif_irq_status[0x1] = 0x%x : sif_irq_status[0x2] = 0x%x : uForceFIQ = 0x%x\n",
|
||||
sif_irq_status[0x0],
|
||||
sif_irq_status[0x1],
|
||||
sif_irq_status[0x2],
|
||||
uForceFIQ
|
||||
);
|
||||
|
||||
/* Only pass events not serviced inline in this isr */
|
||||
|
||||
sif_irq_status[0x0] &= ( MSD_SIF_INTR_IMAGE_DONE_BIT | MSD_SIF_INTR_SLICE_DONE_BIT | MSD_SIF_INTR_SCODE_FOUND_BIT | MSD_SIF_INTR_FORCE_ENTRY_BIT | MSD_SIF_INTR_BSDMA_BIT );
|
||||
sif_irq_status[0x1] &= ( MSD_SIF_INTR2_CSC_BIT | MSD_SIF_INTR2_DFE_DONE_BIT | MSD_SIF_INTR2_DFE_SLC_DONE_BIT | MSD_SIF_INTR2_CQ_BIT);
|
||||
sif_irq_status[0x2] &= ( MSD_SIF_INTR3_DBE0_DONE_BIT | MSD_SIF_INTR3_DBE1_DONE_BIT | MSD_SIF_INTR3_DBE0_SLC_DONE_BIT | MSD_SIF_INTR3_DBE1_SLC_DONE_BIT | MSD_SIF_INTR3_DBE0_CQ_BIT | MSD_SIF_INTR3_DBE1_CQ_BIT );
|
||||
|
||||
/* When passing to thread - explicitly set that a force irq has been set */
|
||||
/* so that the thread function knows after which interrupt it can reset */
|
||||
/* pMVDHw->uForceFIQ */
|
||||
|
||||
sif_irq_status[0x0] |= DECODERLIB_FORCEIRQ_BIT_SET( uForceFIQ );
|
||||
sif_irq_status[0x0] |= DECODERLIB_FORCEDFEIRQ_BIT_SET( uForceDFEFIQ );
|
||||
|
||||
if (( sif_irq_status[0x0] ) ||
|
||||
( sif_irq_status[0x1] ) ||
|
||||
( sif_irq_status[0x2] )
|
||||
)
|
||||
{
|
||||
mvd_kernel_hw_isr_event ( uActMaloneID,
|
||||
sif_irq_status );
|
||||
}
|
||||
}
|
||||
|
||||
/* Future Proof - Restore pgMVDKernelHw */
|
||||
pgMVDKernelHw = pLocMVDHw;
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: mvd_kernel_hw_secondary_isr //
|
||||
// //
|
||||
// DESCRIPTION: Malone HW ISR 2 //
|
||||
// //
|
||||
// INPUTS: irq_val - Identification Parameter from which source of call //
|
||||
// may be ascertained //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: MEDIAIP_IRQ_RETCODE //
|
||||
// //
|
||||
// NOTES: None. //
|
||||
// //
|
||||
// CONTEXT: This function may be called from any context //
|
||||
// Since it is an isr, that may be strange but it can be called to //
|
||||
// handle SW commands in thread context only //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_IRQ_RETCODE mvd_kernel_hw_secondary_isr ( u_int32 irq_val )
|
||||
{
|
||||
u_int32 uActMaloneID;
|
||||
u_int32 uTemp;
|
||||
u_int32 sif_irq_status[0x3] = { 0x0 };
|
||||
#if ( TARGET_APP == GTB_DEC ) || ( TARGET_APP == MEDIA_DEC ) || ( TARGET_APP == VIDEO_TRANS ) || ( TARGET_APP == GTB_TRANS )
|
||||
u_int32 uIrqTarget0, uIrqTarget1;
|
||||
#endif
|
||||
|
||||
/* Future Proof... */
|
||||
/* If we have two levels of interrupt we need to save and restore HW focus */
|
||||
pMALONE_KERNEL_HW_SESSION pLocMVDHw = pgMVDKernelHw;
|
||||
|
||||
/* Work out which Malone instance cause this isr and set HW focus accordingly */
|
||||
|
||||
#if ( TARGET_APP == GTB_DEC ) || ( TARGET_APP == MEDIA_DEC ) || ( TARGET_APP == VIDEO_TRANS ) || ( TARGET_APP == GTB_TRANS )
|
||||
|
||||
pal_int_get_irq_line ( uMvdKernelIrqPin[0x0][0x0],
|
||||
&uIrqTarget0
|
||||
);
|
||||
pal_int_get_irq_line ( uMvdKernelIrqPin[0x0][0x1],
|
||||
&uIrqTarget1
|
||||
);
|
||||
|
||||
uActMaloneID = ( irq_val == MALONE_SW_IRQ ) ? MALONE_SW :
|
||||
(( irq_val == uIrqTarget0 ) | ( irq_val == uIrqTarget1 )) ? MALONE_HW_1 :
|
||||
MALONE_HW_2;
|
||||
|
||||
#else
|
||||
|
||||
uActMaloneID = ( irq_val == MALONE_SW_IRQ ) ? MALONE_SW :
|
||||
(( irq_val == uMvdKernelIrqPin[0x0][0x0] ) | ( irq_val == uMvdKernelIrqPin[0x0][0x1] )) ? MALONE_HW_1 :
|
||||
MALONE_HW_2;
|
||||
|
||||
#endif
|
||||
|
||||
mvd_kernel_hw_set_focus ( uActMaloneID, &pgMVDKernelHw );
|
||||
|
||||
if ( uActMaloneID != MALONE_SW )
|
||||
{
|
||||
/* Break down sif IRQ sources */
|
||||
APB_REG_READ( pgMVDKernelHw->sif_regp->intr_status, sif_irq_status[0x0] );
|
||||
|
||||
/* Clear those we will handle here */
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SIF*/, pgMVDKernelHw->sif_regp->intr_status, sif_irq_status[0x0] & MSD_SIF_INTR2_EXTENSION_BIT_2 );
|
||||
|
||||
/* Read it back to ensure write has made it to Malone */
|
||||
/* Using uActMaloneID as read dsetination as it is no longer */
|
||||
/* required */
|
||||
APB_REG_READ( pgMVDKernelHw->sif_regp->intr_status, uTemp );
|
||||
|
||||
/* Also re-clear the INTC bit which brought us in here since */
|
||||
/* it will have been reset. */
|
||||
pal_int_clear ( irq_val,
|
||||
TRUE );
|
||||
|
||||
if ( sif_irq_status[0x0] & MSD_SIF_INTR2_EXTENSION_BIT_2 )
|
||||
{
|
||||
/* Break down extension IRQ sources */
|
||||
APB_REG_READ( pgMVDKernelHw->sif_regp->intr2_status, sif_irq_status[0x1]);
|
||||
|
||||
/* Clear those we will handle here */
|
||||
MVD_REG_WRITE( pgMVDKernelHw, DECLIB_DBG_REG_SIF, pgMVDKernelHw->sif_regp->intr2_status, sif_irq_status[0x1] & ( MSD_SIF_CTRL2_SPP_SCODE_INTR_ENAB_BIT |
|
||||
MSD_SIF_CTRL2_SPP_PESSC_INTR_ENAB_BIT |
|
||||
MSD_SIF_CTRL2_SPP_BSDMA_INTR_ENAB_BIT ));
|
||||
|
||||
/* Bugzilla 237 - PES Interupt enable inadvertantly set through a RMW of sif_regp->control */
|
||||
if ( sif_irq_status[0x1] & MSD_SIF_CTRL2_SPP_PESSC_INTR_ENAB_BIT )
|
||||
{
|
||||
u_int32 pes_status;
|
||||
|
||||
APB_REG_READ ( pgMVDKernelHw->spp_regp->pes_status, pes_status );
|
||||
|
||||
if ( MSD_SIF_PES_STATUS_GET_STATE( pes_status ) == pes_WaitClear )
|
||||
{
|
||||
/* Pending DTS/PTS looks like it is locked out reception of another startcode */
|
||||
MVD_REG_WRITE( pgMVDKernelHw, 0x0 /*DECLIB_DBG_REG_SPP*/, pgMVDKernelHw->spp_regp->pes_ctrl, 0x0 );
|
||||
}
|
||||
}
|
||||
|
||||
sif_irq_status[0x0] |= DECODERLIB_SECONDARY_ISR_EVENT;
|
||||
|
||||
mvd_kernel_hw_isr_event ( uActMaloneID,
|
||||
sif_irq_status );
|
||||
|
||||
}
|
||||
|
||||
/* What other interrupts might we wish to handle in a seperate context? */
|
||||
/* Only PES is known so far */
|
||||
|
||||
}
|
||||
|
||||
/* Future Proof - Restore pgMVDKernelHw */
|
||||
pgMVDKernelHw = pLocMVDHw;
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: internal_decoder_kernel_lib_isr_event //
|
||||
// //
|
||||
// DESCRIPTION: Callback function for base decoder to schedule the //
|
||||
// processing of the isr in thread context //
|
||||
// //
|
||||
// INPUTS: None //
|
||||
// //
|
||||
// OUTPUTS: None //
|
||||
// //
|
||||
// RETURNS: None //
|
||||
// //
|
||||
// NOTES: Will be called in ISR or thread context by base decoders //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void mvd_kernel_hw_isr_event ( u_int32 uMaloneIdx,
|
||||
u_int32 * puIrqStatus )
|
||||
{
|
||||
DECODER_KERNEL_LIB_ISR_EVENT_DATA sData;
|
||||
|
||||
sData.uMalIdx = uMaloneIdx;
|
||||
sData.uIrqStatus[0x0] = puIrqStatus[0x0];
|
||||
sData.uIrqStatus[0x1] = puIrqStatus[0x1];
|
||||
sData.uIrqStatus[0x2] = puIrqStatus[0x2];
|
||||
|
||||
gDecKernelLib.pfCallback[uMaloneIdx] ( &sData );
|
||||
|
||||
}
|
||||
/* End of file */
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/// @author Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// The code contained herein is licensed under the GNU General Public
|
||||
// License. You may obtain a copy of the GNU General Public License
|
||||
// Version 2 or later at the following locations:
|
||||
//
|
||||
// http://www.opensource.org/licenses/gpl-license.html
|
||||
// http://www.gnu.org/copyleft/gpl.html
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
/// @file DecLib.h
|
||||
/// @brief Main DecLib public header file
|
||||
/// @ingroup DecLib
|
||||
/// @defgroup DecLib DecLib API
|
||||
/// @{
|
||||
/// Decoder Library API level - Exported header file
|
||||
/// called by the Player level and passing data back
|
||||
/// via registered callbacks
|
||||
/// @}
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// $Id:
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "basetype.h"
|
||||
#include "mediaip_fw_types.h"
|
||||
#include "pal.h"
|
||||
#include "DecKernelLibCfg.h"
|
||||
|
||||
#ifndef _DECODER_KLIB_H_
|
||||
#define _DECODER_KLIB_H_
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Macros
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define DECLIB_FSID_INVALID 0xbad
|
||||
|
||||
#define DECLIB_DBG_SESSION_STATE 0x1
|
||||
#define DECLIB_DBG_DECODER_STATE 0x2
|
||||
#define DECLIB_DBG_SYNTAX_ELEMENT 0x4
|
||||
#define DECLIB_DBG_REG_ACCESS 0x8
|
||||
#define DECLIB_DBG_CQ_FIFO 0x10
|
||||
|
||||
#define DECLIB_DBG_REG_HIF 0x1
|
||||
#define DECLIB_DBG_REG_SIF 0x2
|
||||
#define DECLIB_DBG_REG_CTX 0x4
|
||||
#define DECLIB_DBG_REG_RPR 0x8
|
||||
#define DECLIB_DBG_REG_SPP 0x10
|
||||
#define DECLIB_DBG_REG_DEC 0x20
|
||||
#define DECLIB_DBG_REG_CQ 0x40
|
||||
#define DECLIB_DBG_REG_RSB 0x80
|
||||
#define DECLIB_DBG_REG_DFE 0x80
|
||||
|
||||
#ifdef MVD_DIAG_LOG_REG_ACCESS
|
||||
#define DECLIB_DBG_MASK 0x1F
|
||||
#define DECLIB_DBG_REG_MASK 0x1FF
|
||||
#else
|
||||
#define DECLIB_DBG_MASK 0x7
|
||||
#define DECLIB_DBG_REG_MASK 0x0
|
||||
#endif
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Types
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u_int32 uMalIdx;
|
||||
u_int32 uIrqStatus[0x3];
|
||||
|
||||
} DECODER_KERNEL_LIB_ISR_EVENT_DATA;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Function definitions
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
/// Decoder Event info callback
|
||||
|
||||
typedef void ( * DecKernelLib_Isr_Callback_t )( DECODER_KERNEL_LIB_ISR_EVENT_DATA *ptEventData );
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Configuration Type
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
/// DecoderLib Configuration structure
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* Malone hardware details */
|
||||
u_int32 uNumMalones;
|
||||
u_int32 uMaloneHifOffset[DECODERLIB_MAX_MALONES];
|
||||
uint_addr uMaloneBaseAddr[DECODERLIB_MAX_MALONES];
|
||||
u_int32 uMaloneIrqPin[DECODERLIB_MAX_MALONES][0x2];
|
||||
u_int32 uNumDPVUnits; /* 0 or 1 - could infer this from base address but for clarity */
|
||||
uint_addr uDPVBaseAddr;
|
||||
u_int32 uDPVIrqPin;
|
||||
} DECODERLIB_KERNEL_CFG, * pDECODERLIB_KERNEL_CFG;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Function Prototypes
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_FW_STATUS decoder_kernel_lib_init ( DECODERLIB_KERNEL_CFG * pCfg );
|
||||
|
||||
MEDIAIP_FW_STATUS decoder_kernel_lib_term ( void );
|
||||
|
||||
MEDIAIP_FW_STATUS decoder_kernel_lib_register_isr_callback ( u_int32 uMalIdx,
|
||||
DecKernelLib_Isr_Callback_t pfCallback );
|
||||
|
||||
|
||||
#endif /* _DECODER_KLIB_H_ */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Author : Media IP FW team
|
||||
File name : mvd.h
|
||||
Notes : Replaces misnamed "global.h"
|
||||
|
||||
***********************************************/
|
||||
|
||||
#ifndef _MVD_H_
|
||||
#define _MVD_H_
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "basetype.h"
|
||||
#include "DecKernelLibCfg.h"
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Variables
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
extern u_int32 uMvdKernelIrqPin[DECODERLIB_MAX_MALONES][0x2];
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Macros
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Register access model
|
||||
//
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// This is the option used for most builds
|
||||
|
||||
#ifndef MVD_DEBUG_REG_ACCESS
|
||||
#if TARGET_LEVEL == CMODEL
|
||||
extern u_int32 dec_model_malone_reg_write ( u_int32 * puRegAddr, u_int32 uWrtData );
|
||||
extern u_int32 dec_model_malone_reg_read ( u_int32 * puRegAddr, u_int32 uReadData );
|
||||
|
||||
#define APB_REGISTER_WRITE(a,b) dec_model_malone_reg_write ( ( u_int32 * )a, ( u_int32 )b )
|
||||
#define APB_REGISTER_READ(a,b) b = *a; dec_model_malone_reg_read ( ( u_int32 * )a, ( u_int32 )b )
|
||||
#define APB_REG_WRITE(a,b) dec_model_malone_reg_write ( ( u_int32 * )&a, ( u_int32 )b )
|
||||
#define APB_REG_READ(a,b) b = a; dec_model_malone_reg_read ( ( u_int32 * )&a, ( u_int32 )b )
|
||||
#else
|
||||
|
||||
|
||||
|
||||
#if 0
|
||||
#include "VPU_debug.h"
|
||||
//static u_int32 c;
|
||||
|
||||
#define APB_REGISTER_WRITE(a,b) c = b; *a = c; printk("write reg 0x%p, val 0x%x, in %s\n", a, c, __FUNCTION__)
|
||||
#define APB_REGISTER_READ(a,b) c = *a; b = c; printk("read reg 0x%p, val 0x%x, in %s\n", a, c, __FUNCTION__)
|
||||
#define APB_REG_WRITE(a,b) c = b; a = c; printk("write reg 0x%p, val 0x%x, in %s\n", &a, c, __FUNCTION__)
|
||||
#define APB_REG_READ(a,b) c = a; b = c; printk("read reg 0x%p, val 0x%x, in %s\n", &a, c, __FUNCTION__)
|
||||
#else
|
||||
|
||||
#define APB_REGISTER_WRITE(a,b) *a = b
|
||||
#define APB_REGISTER_READ(a,b) b = *a
|
||||
#define APB_REG_WRITE(a,b) a = b
|
||||
#define APB_REG_READ(a,b) b = a
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#else
|
||||
// Store reg acesses in simple debug array for dumping from debugger
|
||||
extern void decoderlib_debug_reg( volatile u_int32 * puRegAddr, u_int32 uVal);
|
||||
#define APB_REGISTER_WRITE(a,b) *a = b
|
||||
#define APB_REGISTER_READ(a,b) b = *a
|
||||
#define APB_REG_WRITE(a,b) decoderlib_debug_reg(( u_int32 * )&a,b)
|
||||
#define APB_REG_READ(a,b) b = a
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef MVD_DIAG_LOG_REG_ACCESS
|
||||
|
||||
#define DIAG_CQ_ID DECLIB_DBG_REG_CQ
|
||||
|
||||
extern void decoderlib_dbg_core_log_write ( volatile u_int32 * puRegAddr, u_int32 uVal, void * pMVDHw, u_int32 uAuxData, bool bActive );
|
||||
extern void decoderlib_dbg_core_log_read ( volatile u_int32 * puRegAddr, u_int32 *puVal, void * pMVDHw, u_int32 uAuxData, bool bActive );
|
||||
extern u_int32 decoderlib_dbg_get_reg_mask ( u_int32 uStrIdx );
|
||||
|
||||
#define MVD_REG_WRITE(pMvdHw,aux,addr,val) decoderlib_dbg_core_log_write ( ( u_int32 * )&addr, val, ( void * )pMvdHw, aux, gbLogRegAccessActive )
|
||||
#define MVD_REG_READ(pMvdHw,aux,addr,val) decoderlib_dbg_core_log_read ( ( u_int32 * )&addr, &val, ( void * )pMvdHw, 0x0, gbLogRegAccessActive )
|
||||
#define MVD_ADDRESS_WRITE(pMvdHw,aux,addr,val) decoderlib_dbg_core_log_write ( ( u_int32 * )addr, val, ( void * )pMvdHw, aux, gbLogRegAccessActive )
|
||||
#define MVD_ADDRESS_READ(pMvdHw,aux,addr,val) decoderlib_dbg_core_log_read ( ( u_int32 * )addr, &val, ( void * )pMvdHw, 0x0, gbLogRegAccessActive )
|
||||
|
||||
#else
|
||||
|
||||
#define MVD_REG_WRITE(pMvdHw,aux,addr,val) APB_REG_WRITE(addr,val)
|
||||
#define MVD_REG_READ(pMvdHw,aux,addr,val) APB_REG_READ(addr,val)
|
||||
#define MVD_ADDRESS_WRITE(pMvdHw,aux,addr,val) APB_REGISTER_WRITE(addr,val)
|
||||
#define MVD_ADDRESS_READ(pMvdHw,aux,addr,val) APB_REGISTER_READ(addr,val)
|
||||
|
||||
#endif /* MVD_DIAG_LOG_REG_WRITES */
|
||||
|
||||
#define APB_REGISTER_POLL(s,p,v,m)
|
||||
#define APB_SEEK_EVENT(e)
|
||||
#define APB_REG_SET(a,m,b) ((a)) = ((((a)) & ~(m)) | ((b) & (m)))
|
||||
|
||||
///////////////////////////
|
||||
// System functions
|
||||
//
|
||||
|
||||
///////////////////////////
|
||||
// MULT_U(a,b)
|
||||
//
|
||||
// a * b
|
||||
|
||||
#define MULT_U(a,b) (a)*(b)
|
||||
|
||||
///////////////////////////
|
||||
// LDIV_MOD_U(a,b)
|
||||
//
|
||||
// a / b, mod = a % b
|
||||
|
||||
#define LDIV_MOD_U(a,b,mod) (a)/(b), mod = (a)%(b)
|
||||
|
||||
///////////////////////////
|
||||
// MEMORY_BLOCK_COPY(a,b,c,d)
|
||||
//
|
||||
// a : int - 1 for load, 0: store
|
||||
// b : int - size of transfer in bytes
|
||||
// c : void * - source address
|
||||
// d : void * - destination address
|
||||
|
||||
#define MEMORY_BLOCK_COPY(a,b,c,d) pal_memcpy(d,c,b)
|
||||
|
||||
//////////////////////////////////////////////////
|
||||
// Implementation running defines
|
||||
//
|
||||
|
||||
#define FORCE_DECODE_HANDLE_IRQ { \
|
||||
pgCtrlMVDHw->uForceFIQ = 1; \
|
||||
if ( pgCtrlMVDHw->uMaloneID == 0 ) \
|
||||
{ \
|
||||
pal_int_set ( uDecLibIrqPin[0x0][0x0] ); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
pal_int_set ( uDecLibIrqPin[0x1][0x0] ); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif /* _MVD_H_ */
|
||||
|
||||
/* End of file */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,975 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Filename: mvd_sif_control.h
|
||||
Description: Malone system interface
|
||||
Notes:
|
||||
|
||||
****************************************************/
|
||||
|
||||
#ifndef _MVD_SIF_CONTROL_H_
|
||||
#define _MVD_SIF_CONTROL_H_
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Macros
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// SIF data range definitions
|
||||
#define MSD_SIF_FS_KBYTES_BITS(r) (((r)&0xFFFF0000)>>16)
|
||||
#define MSD_SIF_FRAME_SIZE_MB_BITS(r) ((r)&0xFFFF)
|
||||
#define MSD_PUT_SIF_FRAME_SIZE_MB_BITS(w) ((w)&0xFFFF)
|
||||
#define MSD_PUT_SIF_FS_KBYTES_BITS(w) (((w)&0xFFFF)<<16)
|
||||
|
||||
#define MSD_PUT_FRAME_WIDTH_MB_BITS(w) ((w)&0xFF)
|
||||
#define MSD_PUT_FRAME_HEIGHT_MB_BITS(w) (((w)&0xFF)<<8)
|
||||
#define MSD_PUT_FRAME_SIZE_MB_BITS(w) (((w)&0xFFFF)<<16)
|
||||
|
||||
#define MSD_DPB_IN_KBYTES_BITS(r) ((r)&0xFFFF)
|
||||
|
||||
#define MPD_SIF_DISP_Q_CNT_BITS(r) ((r)&0xFF)
|
||||
#define MPD_SIF_DISP_Q_FULL_BITS(r) ((r>>8)&0x1)
|
||||
#define MPD_SIF_DISP_Q_REQ_BIT(r) ((r>>16)&0x1)
|
||||
|
||||
#define MPD_SIF_DISP_Q_PUSH_FS_IDC_BITS(w) ((w)&0x1F)
|
||||
#define MPD_SIF_DISP_Q_PUSH_SPS_IDC_BITS(w) (((w)&0x7)<<16)
|
||||
#define MPD_SIF_DISP_Q_PUSH_DANG_FIELD_BIT(w) (((w)&0x1)<<19)
|
||||
#define MPD_SIF_DISP_Q_PUSH_FIELD_MODE_BIT(w) (((w)&0x2)<<19)
|
||||
#define MPD_SIF_DISP_Q_PUSH_BOT_FIRST_BIT(w) (((w)&0x1)<<21)
|
||||
#define MPD_SIF_DISP_Q_PUSH_SKIP_PIC_BITS(w) (((w)&0x3)<<22)
|
||||
#define MPD_SIF_DISP_Q_SYS_DATA_BITS(w) (((w)&0xFF)<<24)
|
||||
|
||||
#define MPD_SIF_DISP_Q_PUSH_CRC_MODE_BIT(w) (((w)&0x1)<<20)
|
||||
|
||||
#define MPD_SIF_FS_PACK_UNIT_BITS(r) ((r)&0x7)
|
||||
#define MPD_SIF_FS_BASE_UNIT_BITS(r) ((r>>12)&0x7)
|
||||
#define MPD_SIF_SYS_DATA_EDGE_BIT(r) ((r>>16)&0x1)
|
||||
#define MPD_SIF_BS_SYNC_USED_BIT(r) ((r>>17)&0x1)
|
||||
|
||||
#define MPD_SIF_SYS_DATA_BITS(r) ((r)&0xFF)
|
||||
|
||||
#define MPD_SIF_FRAME_DEC_IRQ_POS 1
|
||||
#define MPD_SIF_SLICE_DEC_IRQ_POS 2
|
||||
#define MPD_SIF_START_CODE_IRQ_POS 3
|
||||
#define MPD_SIF_SEMAPHORE_IRQ_BIT(r) ((r)&0x1)
|
||||
#define MPD_SIF_FRAME_DEC_IRQ_BIT(r) (((r)&0x2)>>1)
|
||||
#define MPD_SIF_SLICE_DEC_IRQ_BIT(r) (((r)&0x4)>>2)
|
||||
#define MPD_SIF_START_CODE_IRQ_BIT(r) (((r)&0x8)>>3)
|
||||
|
||||
|
||||
#define MSD_SIF_QPULL_IRQ_BIT(r) (((r)&0x10)>>4)
|
||||
#define MSD_SIF_QPULL_SHIFT 4
|
||||
#define MSD_SIF_QPULL_MASK 0x10
|
||||
#define MPD_SIF_BSDMA_IRQ_BIT(r) (((r)&0x80)>>7)
|
||||
#define PUT_MSD_STREAM_ID(w) ((w)&0xF)
|
||||
#define PUT_MSD_FORMAT(w) (((w)&0x3)<<4)
|
||||
|
||||
// Sempahore reg bits
|
||||
#define FRAME_DISPLAYED_BITS(r) ((r)&0x1)
|
||||
|
||||
// MSD_SIF_DPB_FS_SIZE_ADDR
|
||||
#define MSD_SIF_DPB_FS_WIDTH_IN_MB_POS 0
|
||||
#define MSD_SIF_DPB_FS_WIDTH_IN_MB_SIZE 8
|
||||
#define MSD_SIF_DPB_FS_WIDTH_IN_MB_MASK 0xff
|
||||
#define MSD_SIF_DPB_FS_HEIGHT_IN_MB_POS 8
|
||||
#define MSD_SIF_DPB_FS_HEIGHT_IN_MB_SIZE 8
|
||||
#define MSD_SIF_DPB_FS_HEIGHT_IN_MB_MASK 0xff
|
||||
#define MSD_SIF_DPB_FS_SIZE_KBYTES_POS 16
|
||||
#define MSD_SIF_DPB_FS_SIZE_KBYTES_SIZE 14
|
||||
#define MSD_SIF_DPB_FS_SIZE_KBYTES_MASK 0x3fff
|
||||
#define MSD_SIF_DPB_FS_SIZE_WIDTH_INMBS_GET(val) ((val>>MSD_SIF_DPB_FS_WIDTH_IN_MB_POS)&MSD_SIF_DPB_FS_WIDTH_IN_MB_MASK)
|
||||
#define MSD_SIF_DPB_FS_SIZE_HEIGHT_INMBS_GET(val) ((val>>MSD_SIF_DPB_FS_HEIGHT_IN_MB_POS)&MSD_SIF_DPB_FS_HEIGHT_IN_MB_MASK)
|
||||
#define MSD_SIF_DPB_FS_SIZE_KBYTES(val) ((val>>MSD_SIF_DPB_FS_SIZE_KBYTES_POS)&MSD_SIF_DPB_FS_SIZE_KBYTES_MASK)
|
||||
|
||||
// MSD_SIF_DPB_FS_SIZE_EXT_ADDR
|
||||
#define MSD_SIF_DPB_FS_WIDTH_IN_MB_EXT_POS 0
|
||||
#define MSD_SIF_DPB_FS_WIDTH_IN_MB_EXT_SIZE 2
|
||||
#define MSD_SIF_DPB_FS_WIDTH_IN_MB_EXT_MASK 0x3
|
||||
#define MSD_SIF_DPB_FS_HEIGHT_IN_MB_EXT_POS 2
|
||||
#define MSD_SIF_DPB_FS_HEIGHT_IN_MB_EXT_SIZE 2
|
||||
#define MSD_SIF_DPB_FS_HEIGHT_IN_MB_EXT_MASK 0x3
|
||||
#define MSD_SIF_DPB_FS_SIZE_KBYTES_EXT_POS 4
|
||||
#define MSD_SIF_DPB_FS_SIZE_KBYTES_EXT_SIZE 3
|
||||
#define MSD_SIF_DPB_FS_SIZE_KBYTES_EXT_MASK 0x7
|
||||
#define MSD_SIF_DPB_FS_SIZE_WIDTH_INMBS_EXT_GET(val) ((val>>MSD_SIF_DPB_FS_WIDTH_IN_MB_POS)&MSD_SIF_DPB_FS_WIDTH_IN_MB_EXT_MASK)
|
||||
#define MSD_SIF_DPB_FS_SIZE_HEIGHT_INMBS_EXT_GET(val) ((val>>MSD_SIF_DPB_FS_HEIGHT_IN_MB_POS)&MSD_SIF_DPB_FS_HEIGHT_IN_MB_EXT_MASK)
|
||||
#define MSD_SIF_DPB_FS_SIZE_KBYTES_EXT(val) ((val>>MSD_SIF_DPB_FS_SIZE_KBYTES_POS)&MSD_SIF_DPB_FS_SIZE_KBYTES_MASK)
|
||||
|
||||
//MSD_SIF_DPB_FRM_SIZE_ADDR
|
||||
#define MSD_SIF_DPB_FRM_WIDTH_IN_MB_POS 0
|
||||
#define MSD_SIF_DPB_FRM_WIDTH_IN_MB_SIZE 8
|
||||
#define MSD_SIF_DPB_FRM_WIDTH_IN_MB_MASK 0xff
|
||||
#define MSD_SIF_DPB_FRM_HEIGHT_IN_MB_POS 8
|
||||
#define MSD_SIF_DPB_FRM_HEIGHT_IN_MB_SIZE 8
|
||||
#define MSD_SIF_DPB_FRM_HEIGHT_IN_MB_MASK 0xff
|
||||
#define MSD_SIF_DPB_FRM_SIZE_MBS_POS 16
|
||||
#define MSD_SIF_DPB_FRM_SIZE_MBS_SIZE 16
|
||||
#define MSD_SIF_DPB_FRM_SIZE_MBS_MASK 0xffff
|
||||
#define MSD_SIF_DPB_FRM_SIZE_INMBS(val) ((val>>MSD_SIF_DPB_FRM_SIZE_MBS_POS)&MSD_SIF_DPB_FRM_SIZE_MBS_MASK)
|
||||
#define MSD_SIF_DPB_FRM_WIDTH_INMBS_GET(val) ((val>>MSD_SIF_DPB_FRM_WIDTH_IN_MB_POS)&MSD_SIF_DPB_FRM_WIDTH_IN_MB_MASK)
|
||||
#define MSD_SIF_DPB_FRM_HEIGHT_INMBS_GET(val) ((val>>MSD_SIF_DPB_FRM_HEIGHT_IN_MB_POS)&MSD_SIF_DPB_FRM_HEIGHT_IN_MB_MASK)
|
||||
|
||||
//MSD_SIF_DPB_FRM_SIZE_EXT_ADDR
|
||||
#define MSD_SIF_DPB_FRM_WIDTH_IN_MB_EXT_POS 0
|
||||
#define MSD_SIF_DPB_FRM_WIDTH_IN_MB_EXT_SIZE 1
|
||||
#define MSD_SIF_DPB_FRM_WIDTH_IN_MB_EXT_MASK 0x1
|
||||
#define MSD_SIF_DPB_FRM_HEIGHT_IN_MB_EXT_POS 1
|
||||
#define MSD_SIF_DPB_FRM_HEIGHT_IN_MB_EXT_SIZE 1
|
||||
#define MSD_SIF_DPB_FRM_HEIGHT_IN_MB_EXT_MASK 0x1
|
||||
#define MSD_SIF_DPB_FRM_SIZE_MBS_EXT_POS 2
|
||||
#define MSD_SIF_DPB_FRM_SIZE_MBS_EXT_SIZE 3
|
||||
#define MSD_SIF_DPB_FRM_SIZE_MBS_EXT_MASK 0x7
|
||||
#define MSD_SIF_DPB_FRM_SIZE_INMBS_EXT(val) ((val>>MSD_SIF_DPB_FRM_SIZE_MBS_POS)&MSD_SIF_DPB_FRM_WIDTH_IN_MB_EXT_MASK)
|
||||
#define MSD_SIF_DPB_FRM_WIDTH_INMBS_EXT_GET(val) ((val>>MSD_SIF_DPB_FRM_WIDTH_IN_MB_POS)&MSD_SIF_DPB_FRM_HEIGHT_IN_MB_EXT_MASK)
|
||||
#define MSD_SIF_DPB_FRM_HEIGHT_INMBS_EXT_GET(val) ((val>>MSD_SIF_DPB_FRM_HEIGHT_IN_MB_POS)&MSD_SIF_DPB_FRM_SIZE_MBS_EXT_MASK)
|
||||
#define MSD_PUT_FRAME_WIDTH_MB_EXT_BITS(val) (((val>>8)&MSD_SIF_DPB_FRM_WIDTH_IN_MB_EXT_MASK)<<MSD_SIF_DPB_FRM_WIDTH_IN_MB_EXT_POS)
|
||||
#define MSD_PUT_FRAME_HEIGHT_MB_EXT_BITS(val) (((val>>8)&MSD_SIF_DPB_FRM_HEIGHT_IN_MB_EXT_MASK)<<MSD_SIF_DPB_FRM_HEIGHT_IN_MB_EXT_POS)
|
||||
#define MSD_PUT_FRAME_SIZE_MB_EXT_BITS(val) (((val>>16)&MSD_SIF_DPB_FRM_SIZE_MBS_EXT_MASK)<<MSD_SIF_DPB_FRM_SIZE_MBS_EXT_POS)
|
||||
|
||||
|
||||
//MSD_SIF_DPB_FS_SETTING_ADDR
|
||||
#define MSD_SIF_FS_PACK_UNIT_POS 0
|
||||
#define MSD_SIF_FS_PACK_UNIT_SIZE 3
|
||||
#define MSD_SIF_FS_PACK_UNIT(val) ((val>>MSD_SIF_FS_PACK_UNIT_POS)&0x7)
|
||||
#define MSD_SIF_FS_PACK_WIDTH_POS 4
|
||||
#define MSD_SIF_FS_PACK_WIDTH_SIZE 3
|
||||
#define MSD_SIF_FS_PACK_ID (1<<8)
|
||||
#define MSD_SIF_FRM_SYNC_EDGE (1<<16)
|
||||
#define MSD_SIF_BS_SYNC_USED (1<<17)
|
||||
#define MSD_SIF_FS_BASE_UNIT_POS 12
|
||||
#define MSD_SIF_FS_BASE_UNIT(val) ((val>>MSD_SIF_FS_BASE_UNIT_POS)&0x7)
|
||||
|
||||
// Standard pack unit sizes
|
||||
#define SIF_SPB_BASE_UNITS_1KBYTES 0x4
|
||||
#define SIF_SPB_BASE_UNITS_2KBYTES 0x5
|
||||
#define SIF_SPB_BASE_UNITS_4KBYTES 0x6
|
||||
#define SIF_SPB_BASE_UNITS_8KBYTES 0x7
|
||||
|
||||
//MSD_SIF_DPB_OFFSET_ADDR
|
||||
//MSD_SIF_FRM_SYNC_DATA_ADDR
|
||||
//MSD_SIF_FRM_DANGLING_ADDR
|
||||
|
||||
//MSD_SIF_DPB_CONFIG_ADDR
|
||||
#define MSD_SIF_DPB_LUT_ENAB (1<<0)
|
||||
#define MSD_SIF_DPB_LUT_ADDR_MSB (1<<1)
|
||||
#define MSD_SIF_DPB_USE_FS_IDC (1<<2)
|
||||
#define MSD_SIF_DPB_RSHIFT_CA_POS 3
|
||||
#define MSD_SIF_DPB_RSHIFT_CA_SIZE 3
|
||||
|
||||
//MSD_SIF_DPB_LUT_LOAD_ADDR
|
||||
#define MSD_SIF_DPB_LUT_VALUE_POS 0
|
||||
#define MSD_SIF_DPB_LUT_VALUE_SIZE 20
|
||||
#define MSD_SIF_DPB_LUT_ADDR_POS 24
|
||||
#define MSD_SIF_DPB_LUT_ADDR_SIZE 6
|
||||
|
||||
//MSD_SIF_LOAD_DPB_NUMB_ADDR
|
||||
#define MSD_SIF_LOAD_DPB_NUMB_NUMB_POS 0
|
||||
#define MSD_SIF_LOAD_DPB_NUMB_NUMB_SIZE 5
|
||||
#define MSD_SIF_LOAD_DPB_NUMB_NUMB(val) ((val>>MSD_SIF_LOAD_DPB_NUMB_NUMB_POS)&0x1f)
|
||||
#define MSD_SIF_LOAD_DPB_NUMB_SID_POS 12
|
||||
#define MSD_SIF_LOAD_DPB_NUMB_SID_SIZE 4
|
||||
|
||||
//MSD_SIF_DEC_STATUS_ADDR
|
||||
#define MSD_SIF_DEC_STATUS_SLC_PROG_POS 0
|
||||
#define MSD_SIF_DEC_STATUS_SLC_PROG_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_SLC_PROG(val) ((val>>MSD_SIF_DEC_STATUS_SLC_PROG_POS)&0x1)
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_IMG_PROG_POS 1
|
||||
#define MSD_SIF_DEC_STATUS_IMG_PROG_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_IMG_PROG(val) ((val>>MSD_SIF_DEC_STATUS_IMG_PROG_POS)&0x1)
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_FRM_PROG_POS 2
|
||||
#define MSD_SIF_DEC_STATUS_FRM_PROG_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_FRM_PROG(val) ((val>>MSD_SIF_DEC_STATUS_FRM_PROG_POS)&0x1)
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_VPMD_BUSY_POS 3
|
||||
#define MSD_SIF_DEC_STATUS_VPMD_BUSY_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_VPMD_BUSY(val) ((val>>MSD_SIF_DEC_STATUS_VPMD_BUSY_POS)&0x1)
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_VDBF_BUSY_POS 4
|
||||
#define MSD_SIF_DEC_STATUS_VDBF_BUSY_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_VDBF_BUSY(val) ((val>>MSD_SIF_DEC_STATUS_VDBF_BUSY_POS)&0x1)
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_XOB_IDLE_POS 5
|
||||
#define MSD_SIF_DEC_STATUS_XOB_IDLE_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_XOB_IDLE(val) ((val>>MSD_SIF_DEC_STATUS_XOB_IDLE_POS)&0x1)
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_DPBMC_IDLE_POS 6
|
||||
#define MSD_SIF_DEC_STATUS_DPBMC_IDLE_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_DPBMC_IDLE(val) ((val>>MSD_SIF_DEC_STATUS_DPBMC_IDLE_POS)&0x1)
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_BS_EMPTY_POS 7
|
||||
#define MSD_SIF_DEC_STATUS_BS_EMPTY_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_BS_EMPTY(val) ((val>>MSD_SIF_DEC_STATUS_BS_EMPTY_POS)&0x1)
|
||||
|
||||
/* From Kronos Rev.B */
|
||||
#define MSD_SIF_DEC_STATUS_MBQ_STAT_POS 8
|
||||
#define MSD_SIF_DEC_STATUS_MBQ_STAT_SIZE 2
|
||||
#define MSD_SIF_DEC_STATUS_MBQ_STAT(val) ((val>>MSD_SIF_DEC_STATUS_MBQ_STAT_POS)&0x3)
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_MPR_FIFO_POS 10
|
||||
#define MSD_SIF_DEC_STATUS_MPR_FIFO_SIZE 6
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_MPR_FIFOS_NEMPTY_POS 16
|
||||
#define MSD_SIF_DEC_STATUS_MPR_FIFOS_NEMPTY_SIZE 1
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_VMIF_CLSET_IDLE_POS 17
|
||||
#define MSD_SIF_DEC_STATUS_VMIF_CLSET_IDLE_SIZE 2
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_PIXIF_IDLE_POS 19
|
||||
#define MSD_SIF_DEC_STATUS_PIXIF_IDLE_SIZE 1
|
||||
|
||||
#define MSD_SIF_DEC_STATUS_MBIWR_TAGFIFO_EMPTY_POS 22
|
||||
#define MSD_SIF_DEC_STATUS_MBIWR_TAGFIFO_EMPTY_SIZE 1
|
||||
#define MSD_SIF_DEC_STATUS_MBIWR_TAGFIFO_EMPTY(val) ((val>>MSD_SIF_DEC_STATUS_MBIWR_TAGFIFO_EMPTY_POS)&0x1)
|
||||
|
||||
|
||||
//MSD_SIF_BS2RBSP_STATUS_ADDR 6'h32 // R, bs2rbsp status -- [bs_sync frm_sync_data] got_start_code, nal_unit_done, buf_level
|
||||
// BSD data range definitions
|
||||
#define MSD_SIF_BS2RBSP_GOT_START_CODE_BITS(r) ((r)&0x1)
|
||||
#define MSD_SIF_BS2RBSP_NAL_UNIT_DONE_BIT(r) (((r)&0x2)>>1)
|
||||
#define MSD_SIF_BS2RBSP_CBUF_LEVEL_BITS(r) (((r)&0x1FC)>>2)
|
||||
#define MSD_SIF_BS2RBSP_GOT_START_CODE_MASK 0x1
|
||||
#define MSD_SIF_BS2RBSP_GOT_SCODE (1<<0)
|
||||
#define MSD_SIF_BS2RBSP_NALU_FINISH (1<<1)
|
||||
#define MSD_SIF_BS2RBSP_EMPTY (1<<2)
|
||||
#define MSD_SIF_BS2RBSP_BUF_LEVEL_POS 3
|
||||
#define MSD_SIF_BS2RBSP_BUF_LEVEL_SIZE 4
|
||||
#define MSD_SIF_BS2RBSP_BUF_LEVEL(val) ((val>>MSD_SIF_BS2RBSP_BUF_LEVEL_POS)&0xf)
|
||||
#define MSD_SIF_BS2RBSP_GOT_PESSCODE 1<<8
|
||||
#define MSD_SIF_BS2RBSP_SCD_LEVEL_POS 10
|
||||
#define MSD_SIF_BS2RBSP_SCD_LEVEL_MASK 0x3
|
||||
#define MSD_SIF_BS2RBSP_3RD_BTYE_POS 12
|
||||
#define MSD_SIF_BS2RBSP_3RD_BTYE_MASK 0xFF
|
||||
#define MSD_SIF_BS2RBSP_SCD_DIS_POS 20
|
||||
#define MSD_SIF_BS2RBSP_SCD_DIS_MASK 0x1
|
||||
#define MSD_SIF_BS2RBSP_LONG_SCODE_POS 21
|
||||
#define MSD_SIF_BS2RBSP_LONG_SCODE_MASK 0x1
|
||||
#define MSD_SIF_BS2RBSP_SHORT_SYNC_POS 22
|
||||
#define MSD_SIF_BS2RBSP_SHORT_SYNC_MASK 0x1
|
||||
|
||||
#define MSD_SIF_BS2RBSP_SCD_LEVEL(val) ((val >> MSD_SIF_BS2RBSP_SCD_LEVEL_POS ) & MSD_SIF_BS2RBSP_SCD_LEVEL_MASK )
|
||||
#define MSD_SIF_BS2RBSP_SCD_3RD_BTYE(val) ((val >> MSD_SIF_BS2RBSP_3RD_BTYE_POS ) & MSD_SIF_BS2RBSP_3RD_BTYE_MASK )
|
||||
#define MSD_SIF_BS2RBSP_SCD_DIS(val) ((val >> MSD_SIF_BS2RBSP_SCD_DIS_POS ) & MSD_SIF_BS2RBSP_SCD_DIS_MASK )
|
||||
#define MSD_SIF_BS2RBSP_LONG_SCODE(val) ((val >> MSD_SIF_BS2RBSP_LONG_SCODE_POS ) & MSD_SIF_BS2RBSP_LONG_SCODE_MASK )
|
||||
#define MSD_SIF_BS2RBSP_SHORT_SYNC(val) ((val >> MSD_SIF_BS2RBSP_SHORT_SYNC_POS ) & MSD_SIF_BS2RBSP_SHORT_SYNC_MASK )
|
||||
|
||||
//MSD_SIF_BS2RBSP_FEED_ADDR
|
||||
#define MSD_SIF_BS2RBSP_FEED_CTRL (1<<0) // W: RBSP feed start & stop control,
|
||||
#define MSD_SIF_BS2RBSP_NAL_EI_FLAG (1<<1) // R only, on nalu bases, cleared by HW at start of nalu,
|
||||
#define MSD_SIF_BS2RBSP_FEED_STOP ((~MSD_SIF_BS2RBSP_FEED_CTRL)&1)
|
||||
|
||||
//MSD_SIF_BS2RBSP_SCODE_ADDR
|
||||
#define MSD_SIF_BS2RBSP_START_CODE_POS 0
|
||||
#define MSD_SIF_BS2RBSP_START_CODE_SIZE 8
|
||||
#define MSD_SIF_BS2RBSP_START_CODE(val) ((val>>MSD_SIF_BS2RBSP_START_CODE_POS)&0xff)
|
||||
#define MSD_SIF_RS2RBSP_SHORT_SC_POS 8
|
||||
#define MSD_SIF_RS2RBSP_SHORT_SC_SIZE 1
|
||||
#define MSD_SIF_RS2RBSP_SHORT_SC_FLAG(val) ((val>>MSD_SIF_RS2RBSP_SHORT_SC_POS)&0x1)
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA_POS 16
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA(val) ((val & 0xff0000) >> MSD_SIF_BS2RBSP_SYNC_DATA_POS)
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA_SET(val) ((val<<MSD_SIF_BS2RBSP_SYNC_DATA_POS) & 0xff0000)
|
||||
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA_SIZE 8
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA_PTSDTSFLAGS_POS 0
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA_DTS_POS 2
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA_PTS_POS 3
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA_ERR_POS 7
|
||||
#define MSD_SIF_BS2RBSP_SYNC_DATA_ERR (1<<MSD_SIF_BS2RBSP_SYNC_DATA_ERR_POS)
|
||||
#define MSD_SIF_BS2RBSP_SYNC_FLAG (1<<24) // 0 if bs_sync_used is set to '0'
|
||||
|
||||
//MSD_SIF_BS2RBSP_SCDCTRL_ADDR
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_EXPLICIT_CTRL_POS 0
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_ERR_SLCMRG_POS 3
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_DETECT_JPEG_MARKERS_POS 5
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_STOP_SLICE_ON_SYNC_POS 6
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_USE_OLD_EMUL_PREVENT_POS 7
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_SCODE_DETECT_DISABLE_PERIOD_POS 8
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_EXPLICIT_CTRL (1<<MSD_SIF_BS2RBSP_SCDCTRL_EXPLICIT_CTRL_POS)
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_ERR_SLCMRG (1<<MSD_SIF_BS2RBSP_SCDCTRL_ERR_SLCMRG_POS)
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_DETECT_JPEG_MARKERS (1<<MSD_SIF_BS2RBSP_SCDCTRL_DETECT_JPEG_MARKERS_POS)
|
||||
#define MSD_SIF_BS2RBSP_SCDCTRL_STOP_SLICE_ON_SYNC (1<<MSD_SIF_BS2RBSP_SCDCTRL_STOP_SLICE_ON_SYNC_POS)
|
||||
|
||||
//MSD_SIF_CTRL_STATUS_ADDR
|
||||
#define MSD_SIF_CTRL_SEMAPHORE_INTR_BIT (1<<0) // Read Only, '1'
|
||||
#define MSD_SIF_CTRL_IMAGE_INTR_ENAB_BIT (1<<1)
|
||||
#define MSD_SIF_CTRL_SLICE_INTR_ENAB_BIT (1<<2)
|
||||
#define MSD_SIF_CTRL_SCODE_INTR_ENAB_BIT (1<<3)
|
||||
#define MSD_SIF_CTRL_QPULL_INTR_ENAB_BIT (1<<4)
|
||||
#define MSD_SIF_CTRL_DTLERR_INTR_ENAB_BIT (1<<5) // Took over FORCE_ENTRY bit as not needed in status
|
||||
#define MSD_SIF_CTRL_PESSC_INTR_ENAB_BIT (1<<6) // Took over FORCE_ENTRY bit as not needed in status
|
||||
#define MSD_SIF_CTRL_BSDMA_INTR_ENAB_BIT (1<<7)
|
||||
#define MSD_SIF_CTRL_MP2D_SLC_MERGE_BIT (1<<8)
|
||||
#define MSD_SIF_CTRL_BS2RBSP_ENAB_BIT (1<<9)
|
||||
#define MSD_SIF_CTRL_SCODE_IN_FEED_BIT (1<<10)
|
||||
#define MSD_SIF_CTRL_SLC_RESYNC_DISAB_BIT (1<<11)
|
||||
#define MSD_SIF_CTRL_ALT_IRQ_CLR_BIT (1<<12)
|
||||
#define MSD_SIF_CTRL_ASPD_SSC_ENAB_BIT (1<<13) // SPD short start code enable
|
||||
#define MSD_SIF_CTRL_BBB_RSCMD_DISAB_BIT (1<<14) // BBB read-sensitive command disable - if set, BBB get_bits and exp-golumb commands require write first
|
||||
#define MSD_SIF_CTRL_RSBXFR_INTR_ENAB_BIT (1<<15)
|
||||
#define MSD_SIF_CTRL_IRQ_SELECT_BITS_SHIFT (16)
|
||||
|
||||
//MSD_SIF_INTR_STATUS_ADDR
|
||||
#define MSD_SIF_INTR_SEMAPHORE_BIT (1<<0) // Controlled by semaphore interrupt mask, cannot be disabled or forced
|
||||
#define MSD_SIF_INTR_IMAGE_DONE_BIT (1<<1)
|
||||
#define MSD_SIF_INTR_SLICE_DONE_BIT (1<<2)
|
||||
#define MSD_SIF_INTR_SCODE_FOUND_BIT (1<<3)
|
||||
#define MSD_SIF_INTR_DISPQ_PULL_BIT (1<<4)
|
||||
#define MSD_SIF_INTR_FORCE_ENTRY_BIT (1<<5) // Always enabled
|
||||
#define MSD_SIF_INTR_PES_BIT (1<<6)
|
||||
#define MSD_SIF_INTR_BSDMA_BIT (1<<7)
|
||||
#define MSD_SIF_INTR_FORCE_EXIT_BIT (1<<8) // Always enabled
|
||||
#define MSD_SIF_INTR_DTL_ERR_BIT (1<<9)
|
||||
#define MSD_SIF_INTR2_EXTENSION_BITS (3<<10) // Always Enabled
|
||||
#define MSD_SIF_INTR2_EXTENSION_BIT_1 (1<<10) // Always Enabled
|
||||
#define MSD_SIF_INTR2_EXTENSION_BIT_2 (1<<11) // Always Enabled
|
||||
#define MSD_SIF_INTR3_EXTENSION_BITS (3<<12) // Always Enabled
|
||||
#define MSD_SIF_INTR3_EXTENSION_BIT_1 (1<<12) // Always Enabled
|
||||
#define MSD_SIF_INTR3_EXTENSION_BIT_2 (1<<13) // Always Enabled
|
||||
#define MSD_SIF_INTR_RSBXFR_DONE_BIT (1<<15)
|
||||
|
||||
//MSD_SIF_CTRL2_STATUS_ADDR
|
||||
#define MSD_SIF_CTRL2_IRQ_MASK 0x80000000
|
||||
#define MSD_SIF_CTRL2_RPR_DONE_INTR_ENAB_BIT ((1<<4)|MSD_SIF_CTRL2_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL2_BSD_DONE_BIT ((1<<5)|MSD_SIF_CTRL2_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL2_SPP_SCODE_INTR_ENAB_BIT ((1<<6)|MSD_SIF_CTRL2_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL2_SPP_PESSC_INTR_ENAB_BIT ((1<<7)|MSD_SIF_CTRL2_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL2_SPP_BSDMA_INTR_ENAB_BIT ((1<<8)|MSD_SIF_CTRL2_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL2_CSC_DONE_ENAB_BIT ((1<<9) |MSD_SIF_CTRL2_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL2_CQ_ENAB_BIT ((1<<10)|MSD_SIF_CTRL2_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL2_DFE_DONE_ENAB_BIT ((1<<13)|MSD_SIF_CTRL2_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL2_DFE_SLC_DONE_ENAB_BIT ((1<<14)|MSD_SIF_CTRL2_IRQ_MASK)
|
||||
|
||||
//MSD_SIF_INTR2_STATUS_ADDR
|
||||
#define MSD_SIF_INTR2_RPR_BIT (1<<4)
|
||||
#define MSD_SIF_INTR2_SPP_SCODE_FOUND_BIT (1<<6)
|
||||
#define MSD_SIF_INTR2_SPP_PESSC_FOUND_BIT (1<<7)
|
||||
#define MSD_SIF_INTR2_SPP_BSDMA_BIT (1<<8)
|
||||
#define MSD_SIF_INTR2_CSC_BIT (1<<9)
|
||||
#define MSD_SIF_INTR2_CQ_BIT (1<<10)
|
||||
#define MSD_SIF_INTR2_DFE_DONE_BIT (1<<13)
|
||||
#define MSD_SIF_INTR2_DFE_SLC_DONE_BIT (1<<14)
|
||||
|
||||
//MSD_SIF_CTRL3_STATUS_ADDR
|
||||
#define MSD_SIF_CTRL3_IRQ_MASK 0x40000000
|
||||
#define MSD_SIF_CTRL3_DBE0_CQ_ENAB_BIT ((1<<0)|MSD_SIF_CTRL3_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL3_DBE1_CQ_ENAB_BIT ((1<<1)|MSD_SIF_CTRL3_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL3_DBE0_DONE_ENAB_BIT ((1<<4)|MSD_SIF_CTRL3_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL3_DBE1_DONE_ENAB_BIT ((1<<5)|MSD_SIF_CTRL3_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL3_DBE0_SLC_DONE_ENAB_BIT ((1<<8)|MSD_SIF_CTRL3_IRQ_MASK)
|
||||
#define MSD_SIF_CTRL3_DBE1_SLC_DONE_ENAB_BIT ((1<<9)|MSD_SIF_CTRL3_IRQ_MASK)
|
||||
|
||||
//MSD_SIF_INTR3_STATUS_ADDR
|
||||
#define MSD_SIF_INTR3_DBE0_CQ_BIT (1<<0)
|
||||
#define MSD_SIF_INTR3_DBE1_CQ_BIT (1<<1)
|
||||
#define MSD_SIF_INTR3_DBE0_DONE_BIT (1<<4)
|
||||
#define MSD_SIF_INTR3_DBE1_DONE_BIT (1<<5)
|
||||
#define MSD_SIF_INTR3_DBE0_SLC_DONE_BIT (1<<8)
|
||||
#define MSD_SIF_INTR3_DBE1_SLC_DONE_BIT (1<<9)
|
||||
|
||||
//MSD_SIF_RESET_COMMAND_ADDR
|
||||
#define MSD_SIF_RESET_DEC_ENGINE_BIT (1<<0)
|
||||
#define MSD_SIF_RESET_BS_INBUF_BIT (1<<1)
|
||||
#define MSD_SIF_RESET_DISP_QUEUE_BIT (1<<2)
|
||||
#define MSD_SIF_RESET_DTL_CACHE_BIT (1<<3)
|
||||
#define MSD_SIF_RESET_SLICE_BIT (1<<4)
|
||||
#define MSD_SIF_RESET_SPP_BIT (1<<5)
|
||||
#define MSD_SIF_RESET_DTL_4K_CACHE_BIT (1<<6) /* TODO - useme */
|
||||
#define MSD_SIF_RESET_DBE_BIT (1<<7)
|
||||
#define MSD_SIF_RESET_DFE_BIT (1<<8)
|
||||
|
||||
//MSD_CTX_NEXT_SF_ADDR
|
||||
#define MSD_CTX_NEXT_BS_IDC_POS 0
|
||||
#define MSD_CTX_NEXT_BS_IDC_MASK 0xF
|
||||
#define MSD_CTX_NEXT_FORMAT_POS 4
|
||||
#define MSD_CTX_NEXT_FORMAT_MASK 0x1F
|
||||
|
||||
// PES control
|
||||
//volatile u_int32 pes_setup;
|
||||
#define MSD_SIF_PES_SETUP_STRMID_POS 0
|
||||
#define MSD_SIF_PES_SETUP_SET_STRMID(id) ((id&0xff)<<MSD_SIF_PES_SETUP_STRMID_POS)
|
||||
#define MSD_SIF_PES_SETUP_STRMIDMASK_POS 8
|
||||
#define MSD_SIF_PES_SETUP_SET_STRMIDMASK(mask) ((mask&0xff)<<MSD_SIF_PES_SETUP_STRMIDMASK_POS)
|
||||
#define MSD_SIF_PES_SETUP_PESIRQEN_POS 16
|
||||
#define MSD_SIF_PES_SETUP_PESIRQEN (1<<MSD_SIF_PES_SETUP_PESIRQEN_POS)
|
||||
#define MSD_SIF_PES_SETUP_WAITPESHDR_POS 17
|
||||
#define MSD_SIF_PES_SETUP_WAITPESHDR (1<<MSD_SIF_PES_SETUP_WAITPESHDR_POS)
|
||||
#define MSD_SIF_PES_SETUP_ERRORMODE_POS 18
|
||||
#define MSD_SIF_PES_SETUP_SET_ERRORMODE(type) ((type&0x3)<<MSD_SIF_PES_SETUP_ERRORMODE_POS)
|
||||
#define MSD_SIF_PES_SETUP_ERRORMODE_NONE 0x0
|
||||
#define MSD_SIF_PES_SETUP_ERRORMODE_EIFLAG 0x2
|
||||
#define MSD_SIF_PES_SETUP_ERRORMODE_DISCONMARK 0x1
|
||||
#define MSD_SIF_PES_SETUP_PESEN_POS 20
|
||||
#define MSD_SIF_PES_SETUP_PESEN (1<<MSD_SIF_PES_SETUP_PESEN_POS)
|
||||
#define MSD_SIF_PES_SETUP_CHKPKTLEN_POS 21
|
||||
#define MSD_SIF_PES_SETUP_CHKPKTLEN (1<<MSD_SIF_PES_SETUP_CHKPKTLEN_POS)
|
||||
#define MSD_SIF_PES_SETUP_SYNC_ALWAYS_POS 22
|
||||
#define MSD_SIF_PES_SETUP_SYNC_ALWAYS (1<<MSD_SIF_PES_SETUP_SYNC_ALWAYS_POS)
|
||||
#define MSD_SIF_PES_SETUP_HOLD_DODGY_PTS_POS 23
|
||||
#define MSD_SIF_PES_SETUP_HOLD_DODGY_PTS (1<<MSD_SIF_PES_SETUP_HOLD_DODGY_PTS_POS)
|
||||
// Optionally disallow match inside PKT, to support artificial streams that do not have emulation prevention bytes
|
||||
#define MSD_SIF_PES_SETUP_ENFORCE_PKTLEN_POS 24
|
||||
#define MSD_SIF_PES_SETUP_ENFORCE_PKTLEN (1<<MSD_SIF_PES_SETUP_ENFORCE_PKTLEN_POS)
|
||||
|
||||
//volatile u_int32 pes_status;
|
||||
#define MSD_SIF_PES_STATUS_STATE_POS 0
|
||||
#define MSD_SIF_PES_STATUS_GET_STATE(status) ((status>>MSD_SIF_PES_STATUS_STATE_POS)&0x3f)
|
||||
#define MSD_SIF_PES_STATUS_EVENT_POS 6
|
||||
#define MSD_SIF_PES_STATUS_GET_EVENT(status) ((status>>MSD_SIF_PES_STATUS_EVENT_POS)&0x3)
|
||||
#define MSD_SIF_PES_STATUS_PTS_PRESENT 0x2
|
||||
#define MSD_SIF_PES_STATUS_PTSDTS_PRESENT 0x3
|
||||
#define MSD_SIF_PES_STATUS_ERROR_PRESENT 0x1
|
||||
#define MSD_SIF_PES_STATUS_TOPDTS_POS 8
|
||||
#define MSD_SIF_PES_STATUS_GET_TOPDTS(status) ((status>>MSD_SIF_PES_STATUS_TOPDTS_POS)&0x1)
|
||||
#define MSD_SIF_PES_STATUS_SET_TOPDTS(status) ((status & 1) << MSD_SIF_PES_STATUS_TOPDTS_POS)
|
||||
#define MSD_SIF_PES_STATUS_TOPPTS_POS 9
|
||||
#define MSD_SIF_PES_STATUS_GET_TOPPTS(status) ((status>>MSD_SIF_PES_STATUS_TOPPTS_POS)&0x1)
|
||||
#define MSD_SIF_PES_STATUS_SET_TOPPTS(status) ((status & 1) << MSD_SIF_PES_STATUS_TOPPTS_POS)
|
||||
#define MSD_SIF_PES_STATUS_STALLED_POS 10
|
||||
#define MSD_SIF_PES_STATUS_GET_STALLED(status) ((status>>MSD_SIF_PES_STATUS_STALLED_POS)&0x1)
|
||||
#define MSD_SIF_PES_STATUS_STREAM_ID_MASK 0xFF
|
||||
#define MSD_SIF_PES_STATUS_STREAM_ID_POS 12
|
||||
#define MSD_SIF_PES_STATUS_GET_STREAMID(status) ((status>>MSD_SIF_PES_STATUS_STREAM_ID_POS)&MSD_SIF_PES_STATUS_STREAM_ID_MASK)
|
||||
#define MSD_SIF_PES_STATUS_TIMEBASE_ID_MASK 0x7
|
||||
#define MSD_SIF_PES_STATUS_TIMEBASE_ID_POS 12
|
||||
#define MSD_SIF_PES_STATUS_GET_TIMEBASE(status) ((status>>MSD_SIF_PES_STATUS_TIMEBASE_ID_POS)&MSD_SIF_PES_STATUS_TIMEBASE_ID_MASK)
|
||||
#define MSD_SIF_PES_STATUS_PARITY_MASK 0x1
|
||||
#define MSD_SIF_PES_STATUS_PARITY_POS 15
|
||||
#define MSD_SIF_PES_STATUS_GET_PARITY(status) ((status>>MSD_SIF_PES_STATUS_PARITY_POS)&MSD_SIF_PES_STATUS_PARITY_MASK)
|
||||
|
||||
typedef enum
|
||||
{
|
||||
pes_Seek = 4, // 6'b0001_00, // Wait for initial start pes start code
|
||||
pes_DumpPrefix = 8, // 6'b0010_00, // Dumping the 0x00_00_01. Move on when get the 0x01
|
||||
pes_DumpStrmID = 12, // 6'b0011_00, // Dumping the 0x00_00_01. Move on when get the 0x01
|
||||
pes_WaitClear = 16, // 6'b0100_00, // Stalled waiting for firmware to clear the previous PTS
|
||||
pes_PackLenH = 20, // 6'b0101_00, //
|
||||
pes_PackLenL = 24, // 6'b0110_00, //
|
||||
pes_Discon_0 = 28, // 6'b0111_00, // Output 0x00 from internally generates discontinuity
|
||||
pes_Discon_1 = 32, // 6'b1000_00, // Output 0x00
|
||||
pes_Discon_2 = 36, // 6'b1001_00, // Output 0x01
|
||||
pes_Discon_3 = 40, // 6'b1010_00, // Output 0xB4
|
||||
pes_ParseFW = 60, // 6'b1111_00, // Just let firmware read the data one at a time
|
||||
pes_Flags1 = 1, // 6'b0000_01,
|
||||
pes_Flags2 = 5, // 6'b0001_01,
|
||||
pes_HdrLen = 9, // 6'b0010_01,
|
||||
pes_PTS1 = 3, // 6'b0000_11,
|
||||
pes_PTS2 = 7, // 6'b0001_11,
|
||||
pes_PTS3 = 11, // 6'b0010_11,
|
||||
pes_PTS4 = 15, // 6'b0011_11,
|
||||
pes_PTS5 = 19, // 6'b0100_11,
|
||||
pes_DTS1 = 23, // 6'b0101_11,
|
||||
pes_DTS2 = 27, // 6'b0110_11,
|
||||
pes_DTS3 = 31, // 6'b0111_11,
|
||||
pes_DTS4 = 35, // 6'b1000_11,
|
||||
pes_DTS5 = 39, // 6'b1001_11,
|
||||
pes_DumpHdr = 43, // 6'b1010_11, // Skipping over remainder of headre
|
||||
pes_PayloadSync = 45, // 6'b1011_01, // Outputting first payload byte to SCD
|
||||
pes_Payload = 49 // 6'b1100_01 // Outputting payload to SCD
|
||||
|
||||
} PES_STATE;
|
||||
|
||||
// BSDMA Control
|
||||
//volatile u_int32 bsdma_command;
|
||||
#define MSD_SIF_BSDMA_CMND_START 0x1
|
||||
#define MSD_SIF_BSDMA_CMND_FETCHSTRDESC 0x2
|
||||
#define MSD_SIF_BSDMA_CMND_STOP 0x4
|
||||
#define MSD_SIF_BSDMA_CMND_CLEAR 0x8
|
||||
#define MSD_SIF_BSDMA_CMND_FORCE_DESC_UPDATE 0x10
|
||||
#define MSD_SIF_BSDMA_CMND_FORCE_CALC_LEVEL 0x20
|
||||
|
||||
//volatile u_int32 bsdma_options;
|
||||
#define MSD_SIF_BSDMA_OPT_ENABLE 0x1
|
||||
#define MSD_SIF_BSDMA_OPT_PERIEN 0x2
|
||||
#define MSD_SIF_BSDMA_OPT_OFLIRQEN 0x4
|
||||
#define MSD_SIF_BSDMA_OPT_DISCONEN 0x8
|
||||
#define MSD_SIF_BSDMA_OPT_DESCUPPER_POS 4
|
||||
#define MSD_SIF_BSDMA_OPT_LOCBUFSIZE_POS 8
|
||||
#define MSD_SIF_BSDMA_OPT_LOCBUFOFFSET_POS 16
|
||||
#define MSD_SIF_BSDMA_OPT_DEBUG_FEED (1<<24)
|
||||
#define MSD_SIF_BSDMA_OPT_BURST (1<<25)
|
||||
|
||||
#define MSD_SIF_BSDMA_OPT_SAFEREADMARGIN_POS 26
|
||||
#define MSD_SIF_BSDMA_OPT_TRACEBACK_POS 28
|
||||
#define MSD_BSDMA_STRIDE_END_IRQ_P0S 30 // Interrupt when all data read
|
||||
#define MSD_BSDMA_STRIDE_END_IRQ (1<<MSD_BSDMA_STRIDE_END_IRQ_P0S)
|
||||
#define MSD_BSDMA_STRIDE_DONE_IRQ_POS 31 // Interrupt when all data used
|
||||
#define MSD_BSDMA_STRIDE_DONE_IRQ ((u_int32)(1<<MSD_BSDMA_STRIDE_DONE_IRQ_POS))
|
||||
|
||||
|
||||
#define MSD_SIF_BSDMA_OPT_0B_SAFEMARGIN (0<<MSD_SIF_BSDMA_OPT_SAFEREADMARGIN_POS)
|
||||
#define MSD_SIF_BSDMA_OPT_128B_SAFEMARGIN (1<<MSD_SIF_BSDMA_OPT_SAFEREADMARGIN_POS)
|
||||
#define MSD_SIF_BSDMA_OPT_2KB_SAFEMARGIN (2<<MSD_SIF_BSDMA_OPT_SAFEREADMARGIN_POS)
|
||||
#define MSD_SIF_BSDMA_OPT_32KB_SAFEMARGIN (3<<MSD_SIF_BSDMA_OPT_SAFEREADMARGIN_POS)
|
||||
|
||||
#define MSD_SIF_BSDMA_OPT_TRACEBACK_0 (0<<MSD_SIF_BSDMA_OPT_TRACEBACK_POS)
|
||||
#define MSD_SIF_BSDMA_OPT_TRACEBACK_16K (1<<MSD_SIF_BSDMA_OPT_TRACEBACK_POS)
|
||||
#define MSD_SIF_BSDMA_OPT_TRACEBACK_256K (2<<MSD_SIF_BSDMA_OPT_TRACEBACK_POS)
|
||||
#define MSD_SIF_BSDMA_OPT_TRACEBACK_4M (3<<MSD_SIF_BSDMA_OPT_TRACEBACK_POS)
|
||||
|
||||
/* Constant defines on the 160/128 64-bit words of IBB memory */
|
||||
/* Split between the BSDMA stream buffer and the H.264 IBB usage */
|
||||
#define IBBBUF_SIZE 128
|
||||
#define IBBBUF_SIZE_LARGE 160
|
||||
#define BSDMA_IBBBUF_USAGE 16
|
||||
|
||||
//volatile u_int32 bsdma_status;
|
||||
#define MSD_SIF_BSDMA_STATUS_CB_LEVEL (0xFF)
|
||||
#define MSD_SIF_BSDMA_STATUS_NMEMWORDS (0x1f<<8)
|
||||
#define MSD_SIF_BSDMA_STATUS_BELOW_LWM (0x1<<13) // Currently below Low Water Mark
|
||||
#define MSD_SIF_BSDMA_STATUS_BELOW_LWMH (0x1<<14) // Below Low Water Mark since last cleared
|
||||
#define MSD_SIF_BSDMA_STATUS_BUFOFLOW (0x1<<15)
|
||||
#define MSD_SIF_BSDMA_STATUS_DMA_STATE (0x1F<<16)
|
||||
#define MSD_SIF_BSDMA_STATUS_MCX_STATE (0x3F<<21)
|
||||
#define MSD_SIF_BSDMA_STATUS_RQ_STATE (0x1<<27)
|
||||
#define MSD_SIF_BSDMA_STATUS_ABOVE_HWM (0x1<<28) // Currently above High Water Mark
|
||||
#define MSD_SIF_BSDMA_STATUS_ABOVE_HWMH (0x1<<29) // Above High Water Mark since last cleared
|
||||
#define MSD_SIF_BSDMA_STATUS_STRIDE_END (0x1<<30) // all data fed
|
||||
#define MSD_SIF_BSDMA_STATUS_STRIDE_DONE ((u_int32)(0x1<<31)) // all data used
|
||||
|
||||
#define MSD_SIF_BSDMA_EXTOPT_LOOPBIT_POS 0x0
|
||||
#define MSD_SIF_BSDMA_EXTOPT_CB_MIN_POS 3
|
||||
#define MSD_SIF_BSDMA_EXTOPT_REQ_8 (1<<10)
|
||||
#define MSD_SIF_BSDMA_EXTOPT_SINGLE_STRIDE (1<<11)
|
||||
#define MSD_SIF_BSDMA_EXTOPT_INIT_IRQ (1<<12)
|
||||
#define MSD_SIF_BSDMA_EXTOPT_MIN_UPDATES (1<<13)
|
||||
#define MSD_SIF_BSDMA_EXTOPT_CHECK_WPTR (1<<14)
|
||||
|
||||
//volatile u_int32 bsdma_ext_options;
|
||||
#define MSD_SIF_BSDMA_EXTOPT_LOOPBIT_SET(w) ((w&0x7)<<MSD_SIF_BSDMA_EXTOPT_LOOPBIT_POS)
|
||||
#define MSD_SIF_BSDMA_EXTOPT_LOOPBIT_GET(r) ((r>>MSD_SIF_BSDMA_EXTOPT_LOOPBIT_POS)&0x7)
|
||||
#define MSD_SIF_BSDMA_EXTOPT_SINGLESHOTEXITMODE MSD_SIF_BSDMA_EXTOPT_SINGLE_STRIDE
|
||||
|
||||
// This define is used only when FW controls how close the RP can get to the WP
|
||||
// For pecos we are assuming at least two full burst of distance
|
||||
//#define BSDMA_WP_AHEAD_OF_RP_MARGIN (2*16*8)
|
||||
#define BSDMA_WP_AHEAD_OF_RP_MARGIN (8*16*8)
|
||||
#define BSDMA_DESC_REAL_ADDR(x) (x&0xfffffff)
|
||||
#define BSDMA_DESC_WRAP_ADDR(x) (x&0xf0000000)
|
||||
#define BSDMA_DESC_NOPARITY_MASK 0xfffffffe
|
||||
|
||||
|
||||
#define MSD_FORMAT_H264 (0x1 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_VC1 (0x2 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_MP2 (0x3 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_AVS (0x4 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_ASP (0x5 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_JPG (0xD <<MSD_CTX_NEXT_FORMAT_POS) // Uses aspd HW and ext. format flag
|
||||
#define MSD_FORMAT_RV8 (0x6 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_RV9 (0xE <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_VP6 (0x7 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_VP8 (0xF <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_VP3 (0x7 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_HEVC (0x10 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
#define MSD_FORMAT_NULL (0x0 <<MSD_CTX_NEXT_FORMAT_POS)
|
||||
|
||||
//MSD_SIF_DPBMC_SETUP_ADDR
|
||||
#define MSD_SIF_DPBMC_SET_CRC_TYPE(datasrc,datatype) (((0x3&datatype)<<2)|(datasrc&0x3))
|
||||
|
||||
#define MSD_SIF_DPBMC_CLEAR_CRC2_TYPE_MASK 0xFF0FFFFF
|
||||
#define MSD_SIF_DPBMC_SET_CRC2_TYPE(datasrc,datatype) (((0x3&datatype)<<22)|((datasrc&0x3)<<20))
|
||||
// Alternate method of setup
|
||||
|
||||
#define MSD_SIF_DPBMC_CLEAR_CRC2_MAJOR_MINOR_TYPE_MASK 0x87CFFFFF
|
||||
#define MSD_SIF_DPBMC_SET_CRC2_TYPE_MAJOR(datatype) (( 0x3 & datatype ) << 20 )
|
||||
#define MSD_SIF_DPBMC_SET_CRC2_TYPE_MINOR(datasrc) (( 0xf & datasrc ) << 27 )
|
||||
#define MSD_SIF_DPBMC_GET_CRC2_TYPE_MAJOR(datatype) (( datatype >> 20 ) & 0x3 )
|
||||
#define MSD_SIF_DPBMC_GET_CRC2_TYPE_MINOR(datasrc) (( datasrc >> 27) & 0xf )
|
||||
#define MSD_SIF_DPBMC_SET_CRC_ALT_TYPE_MAJOR(datatype) (( 0x3 & datatype ) << 2 )
|
||||
#define MSD_SIF_DPBMC_SET_CRC_ALT_TYPE_MINOR(datasrc) (( 0xf & datasrc ) << 23 )
|
||||
#define MSD_SIF_DPBMC_SET_CRC_USE_ALT_TYPE(use) (( use & 0x1 ) << 22 )
|
||||
|
||||
#define MSD_SIF_DPBMC_CRC_RDDATA_TYPE 0x0
|
||||
#define MSD_SIF_DPBMC_CRC_WRDATA_TYPE 0x1
|
||||
#define MSD_SIF_DPBMC_CRC_RDADDR_TYPE 0x2
|
||||
#define MSD_SIF_DPBMC_CRC_WRADDR_TYPE 0x3
|
||||
#define MSD_SIF_DPBMC_CRC_BPP_SRCTYPE 0x3
|
||||
#define MSD_SIF_DPBMC_CRC_MBI_SRCTYPE 0x2
|
||||
#define MSD_SIF_DPBMC_CRC_PIXEL_SRCTYPE 0x0
|
||||
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_DBE1_SRCTYPE 0xf
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_TES_SRCTYPE 0xe
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_DFE_SRCTYPE 0xd
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_MPSDBF_UV_SRCTYPE 0xc
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_SVC_RSMP_SRCTYPE 0xb
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_SVC_META_SRCTYPE 0xa
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_MBQ_SRCTYPE 0x9
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_CSC_SRCTYPE 0x8
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_RPR_SRCTYPE 0x7
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_MPSDBF_SRCTYPE 0x6
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_MBI_SRCTYPE 0x5
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_MX12_SRCTYPE 0x4
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_MX34_SRCTYPE 0x3
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_RSB_SRCTYPE 0x2
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_MCX_SRCTYPE 0x1
|
||||
#define MSD_SIF_DPBMC_CRC_ALT_BSD_SRCTYPE 0x0
|
||||
|
||||
#define MSD_SIF_DPBMC_OUTSTAND_REQ_POS 4
|
||||
#define MSD_SIF_DPBMC_OUTSTAND_REQ_MASK 0x7
|
||||
#define MSD_SIF_DPBMC_SET_OUTSTAND_REQ(num_req) ((num_req&MSD_SIF_DPBMC_OUTSTAND_REQ_MASK)<<MSD_SIF_DPBMC_OUTSTAND_REQ_POS)
|
||||
#define MSD_SIF_DPBMC_OUTSTAND_WR_REQ_POS 7
|
||||
#define MSD_SIF_DPBMC_OUTSTAND_WR_REQ_MASK 0x3
|
||||
#define MSD_SIF_DPBMC_SET_OUTSTAND_WR_REQ(num_req) ((num_req&MSD_SIF_DPBMC_OUTSTAND_WR_REQ_MASK)<<MSD_SIF_DPBMC_OUTSTAND_WR_REQ_POS)
|
||||
#define MSD_SIF_DPBMC_DBFAL_MODE_POS 9
|
||||
#define MSD_SIF_DPBMC_DBFAL_MODE_MASK 0x3
|
||||
#define MSD_SIF_DPBMC_SET_DBFAL_MODE(num_req) ((num_req&MSD_SIF_DPBMC_DBFAL_MODE_MASK)<<MSD_SIF_DPBMC_DBFAL_MODE_POS)
|
||||
#define MSD_SIF_DPBMC_SET_USE_CHROMA_DPATH_POS 0x0
|
||||
#define MSD_SIF_DPBMC_SET_USE_CHROMA_DPATH_MASK 0x1
|
||||
#define MSD_SIF_DPBMC_SET_USE_CHROMA_DPATH(a) ((a&MSD_SIF_DPBMC_SET_USE_CHROMA_DPATH_MASK)<<MSD_SIF_DPBMC_SET_USE_CHROMA_DPATH_POS)
|
||||
#define MSD_SIF_DPBMC_SET_CLR_CHROMA_DPATH (~(MSD_SIF_DPBMC_SET_USE_CHROMA_DPATH_MASK << MSD_SIF_DPBMC_SET_USE_CHROMA_DPATH_POS))
|
||||
|
||||
|
||||
// VMIF MBI CACHE
|
||||
#define MSD_VMIF_MBI_CACHE_RDCLR_POS 0
|
||||
#define MSD_VMIF_MBI_CACHE_RDCLR_MASK 0x7
|
||||
#define MSD_VMIF_MBI_CACHE_RDDIS_POS 3
|
||||
#define MSD_VMIF_MBI_CACHE_RDDIS_MASK 0x7
|
||||
#define MSD_VMIF_MBI_CACHE_RDSCLR_DIS_POS 6
|
||||
#define MSD_VMIF_MBI_CACHE_RDSCLR_DIS_MASK 0x7
|
||||
#define MSD_VMIF_MBI_CACHE_WRCLR_POS 9
|
||||
#define MSD_VMIF_MBI_CACHE_WRCLR_MASK 0x7
|
||||
#define MSD_VMIF_MBI_CACHE_WRDIS_POS 12
|
||||
#define MSD_VMIF_MBI_CACHE_WRDIS_MASK 0x7
|
||||
#define MSD_VMIF_MBI_CACHE_WRFLSH_POS 15
|
||||
#define MSD_VMIF_MBI_CACHE_WRFLSH_MASK 0x7
|
||||
|
||||
#define MSD_VMIF_MBI_CACHE_SET_RDCLR(w) ((w&MSD_VMIF_MBI_CACHE_RDCLR_MASK)<<MSD_VMIF_MBI_CACHE_RDCLR_POS)
|
||||
#define MSD_VMIF_MBI_CACHE_SET_RDDIS(w) ((w&MSD_VMIF_MBI_CACHE_RDDIS_MASK)<<MSD_VMIF_MBI_CACHE_RDDIS_POS)
|
||||
#define MSD_VMIF_MBI_CACHE_SET_RDSCLR_DIS(w) ((w&MSD_VMIF_MBI_CACHE_RDSCLR_DIS_MASK)<<MSD_VMIF_MBI_CACHE_RDSCLR_DIS_POS)
|
||||
#define MSD_VMIF_MBI_CACHE_SET_WRCLR(w) ((w&MSD_VMIF_MBI_CACHE_WRCLR_MASK)<<MSD_VMIF_MBI_CACHE_WRCLR_POS)
|
||||
#define MSD_VMIF_MBI_CACHE_SET_WRDIS(w) ((w&MSD_VMIF_MBI_CACHE_WRDIS_MASK)<<MSD_VMIF_MBI_CACHE_WRDIS_POS)
|
||||
#define MSD_VMIF_MBI_CACHE_SET_WRFLSH(w) ((w&MSD_SIF_DPBMC_OUTSTAND_WR_REQ_MASK)<<MSD_VMIF_MBI_CACHE_WRFLSH_POS)
|
||||
|
||||
|
||||
// DPBMC SETUP 2
|
||||
#define MSD_SIF_DPBMC_SET_OUTSTAND_MBIRD_MASK 0x3
|
||||
#define MSD_SIF_DPBMC_SET_OUTSTAND_MBIRD_POS 14
|
||||
#define MSD_VMIF_MPSAL_MODE_DISOB_BIT 13
|
||||
#define MSD_VMIF_MPSAL_MODE_REQ16_BIT 10
|
||||
#define MSD_VMIF_MPSAL_MODE_16PIX_POS 9
|
||||
// MSD_SIF_COUNT_STRB_SEL_BITS 8:1
|
||||
#define MSD_SIF_COUNT_RD_CMD_STRB_SEL 7
|
||||
#define MSD_SIF_COUNT_WR_CMD_STRB_SEL 6
|
||||
#define MSD_SIF_COUNT_WR_STRB_SEL 5
|
||||
#define MSD_SIF_COUNT_RD_STRB_SEL 4
|
||||
#define MSD_SIF_COUNT_UV_RD_STRB_SEL 3
|
||||
#define MSD_SIF_COUNT_RSMP_RD_STRB_SEL 2
|
||||
#define MSD_SIF_COUNT_RSMP_MBMETA_STRB_SEL 1
|
||||
#define MSD_SIF_COUNT_MBI_RD_STRB_SEL 0
|
||||
|
||||
#define MSD_SIF_COUNT_STRB_SEL_MASK 0x1
|
||||
#define MSD_SIF_COUNT_STRB_SET_USE_RD_CMD_STRB(a) (((a&MSD_SIF_COUNT_STRB_SEL_MASK) <<MSD_SIF_COUNT_RD_CMD_STRB_SEL )<<1)
|
||||
#define MSD_SIF_COUNT_STRB_SET_USE_WR_CMD_STRB(a) (((a&MSD_SIF_COUNT_STRB_SEL_MASK) <<MSD_SIF_COUNT_WR_CMD_STRB_SEL )<<1)
|
||||
#define MSD_SIF_COUNT_STRB_SET_USE_WR_STRB(a) (((a&MSD_SIF_COUNT_STRB_SEL_MASK) <<MSD_SIF_COUNT_WR_STRB_SEL )<<1)
|
||||
#define MSD_SIF_COUNT_STRB_SET_USE_RD_STRB(a) (((a&MSD_SIF_COUNT_STRB_SEL_MASK) <<MSD_SIF_COUNT_RD_STRB_SEL )<<1)
|
||||
#define MSD_SIF_COUNT_STRB_SET_USE_UV_RD_STRB(a) (((a&MSD_SIF_COUNT_STRB_SEL_MASK) <<MSD_SIF_COUNT_UV_RD_STRB_SEL )<<1)
|
||||
#define MSD_SIF_COUNT_STRB_SET_USE_RSMP_RD_STRB(a) (((a&MSD_SIF_COUNT_STRB_SEL_MASK) <<MSD_SIF_COUNT_RSMP_RD_STRB_SEL )<<1)
|
||||
#define MSD_SIF_COUNT_STRB_SET_USE_RSMP_MBMETA_STRB(a) (((a&MSD_SIF_COUNT_STRB_SEL_MASK) <<MSD_SIF_COUNT_RSMP_MBMETA_STRB_SEL )<<1)
|
||||
#define MSD_SIF_COUNT_STRB_SET_USE_MBI_RD_STRB(a) (((a&MSD_SIF_COUNT_STRB_SEL_MASK) <<MSD_SIF_COUNT_MBI_RD_STRB_SEL )<<1)
|
||||
#define MSD_SIF_DPBMC_SET_OUTSTAND_MBIRD(a) ((a&MSD_SIF_DPBMC_SET_OUTSTAND_MBIRD_MASK)<<MSD_SIF_DPBMC_SET_OUTSTAND_MBIRD_POS)
|
||||
|
||||
|
||||
#define MSD_DPBMC_DPBCOH_POS 9
|
||||
#define MSD_DPBMC_DPBCOH_MASK 0x1
|
||||
#define MSD_DPBMC_DPBCOH_SET(a) ((a&MSD_DPBMC_DPBCOH_MASK)<<MSD_DPBMC_DPBCOH_POS)
|
||||
#define MSD_DPBMC_MBICOH_POS 10
|
||||
#define MSD_DPBMC_MBICOH_MASK 0x1
|
||||
#define MSD_DPBMC_MBICOH_SET(a) ((a&MSD_DPBMC_MBICOH_MASK)<<MSD_DPBMC_MBICOH_POS)
|
||||
#define MSD_DPBMC_RSBCOH_POS 11
|
||||
#define MSD_DPBMC_RSBCOH_MASK 0x1
|
||||
#define MSD_DPBMC_RSBCOH_SET(a) ((a&MSD_DPBMC_RSBCOH_MASK)<<MSD_DPBMC_RSBCOH_POS)
|
||||
#define MSD_SIF_DPBMC_BASE_UNIT_POS 12
|
||||
#define MSD_SIF_DPBMC_BASE_UNIT_MASK 0x7
|
||||
#define MSD_SIF_DPBMC_SET_BASE_UNIT(base) ((base&MSD_SIF_DPBMC_BASE_UNIT_MASK)<<MSD_SIF_DPBMC_BASE_UNIT_POS)
|
||||
#define MSD_DPBMC_INT_WAIT_IDLE_POS 15
|
||||
#define MSD_DPBMC_INT_WAIT_IDLE_MASK 0x1
|
||||
#define MSD_DPBMC_INT_WAIT_IDLE_SET(a) ((a&MSD_DPBMC_INT_WAIT_IDLE_MASK)<<MSD_DPBMC_INT_WAIT_IDLE_POS)
|
||||
#define MSD_DPBMC_SC_INT_WAIT_IDLE_SET_POS 31
|
||||
#define MSD_DPBMC_SC_INT_WAIT_IDLE_SET_MASK 0x1
|
||||
#define MSD_DPBMC_SC_INT_WAIT_IDLE_SET(a) ((a&MSD_DPBMC_SC_INT_WAIT_IDLE_SET_MASK)<<MSD_DPBMC_SC_INT_WAIT_IDLE_SET_POS)
|
||||
#define MSD_DPBMC_ARB_MCX_POS 16
|
||||
#define MSD_DPBMC_ARB_MCX_MASK 0x1
|
||||
#define MSD_DPBMC_ARB_MCX_SET(a) ((a&MSD_DPBMC_ARB_MCX_MASK)<<MSD_DPBMC_ARB_MCX_POS)
|
||||
#define MSD_DPBMC_ARB_MCX_CLR(a) (~((a&MSD_DPBMC_ARB_MCX_MASK)<<MSD_DPBMC_ARB_MCX_POS))
|
||||
#define MSD_DPBMC_ARB_BSDMA_POS 17
|
||||
#define MSD_DPBMC_ARB_BSDMA_MASK 0x1
|
||||
#define MSD_DPBMC_ARB_BSDMA_SET(a) ((a&MSD_DPBMC_ARB_BSDMA_MASK)<<MSD_DPBMC_ARB_BSDMA_POS)
|
||||
#define MSD_DPBMC_ARB_BSDMA_CLR(a) (~((a&MSD_DPBMC_ARB_BSDMA_MASK)<<MSD_DPBMC_ARB_BSDMA_POS))
|
||||
#define MSD_DPBMC_DIS_CRC_AUTO_RESET_POS 19
|
||||
#define MSD_DPBMC_DIS_CRC_AUTO_RESET_MASK 0x1
|
||||
#define MSD_DPBMC_DIS_CRC_AUTO_RESET_SET(a) ((a&MSD_DPBMC_DIS_CRC_AUTO_RESET_MASK)<<MSD_DPBMC_DIS_CRC_AUTO_RESET_POS)
|
||||
#define MSD_DPBMC_DIS_CRC_AUTO_RESET_CLR(a) (~((a&MSD_DPBMC_DIS_CRC_AUTO_RESET_MASK)<<MSD_DPBMC_DIS_CRC_AUTO_RESET_POS))
|
||||
|
||||
// Local memory configuration (power down)
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_MASK 0x1
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_CCHE0_POS 0
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_RSB_POS 1
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_AVSD_POS 2
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_MPGD_POS 3
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_VC1D_POS 4
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_AVCD_POS 5
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_COMM_POS 6
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_RPR_POS 7
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_CCHE1_POS 14
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_HEVD_POS 15
|
||||
#define MSD_SIF_LMEM_CONFIG_PD_VMIF_POS 17
|
||||
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_CCHE0(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_CCHE0_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_RSB(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_RSB_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_AVSD(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_AVSD_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_MPGD(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_MPGD_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_VC1D(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_VC1D_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_AVCD(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_AVCD_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_COMM(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_COMM_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_RPR(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_RPR_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_CCHE1(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_CCHE1_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_HEVD(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_HEVD_POS )
|
||||
#define MSD_SIF_LMEM_CONFIG_SET_PD_VMIF(a) ((a&MSD_SIF_LMEM_CONFIG_PD_MASK) <<MSD_SIF_LMEM_CONFIG_PD_VMIF_POS )
|
||||
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_CCHE0(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_CCHE0_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_RSB(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_RSB_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_AVSD(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_AVSD_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_MPGD(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_MPGD_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_VC1D(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_VC1D_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_AVCD(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_AVCD_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_COMM(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_COMM_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_RPR(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_RPR_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_CCHE1(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_CCHE1_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_HEVD(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_HEVD_POS )))
|
||||
#define MSD_SIF_LMEM_CONFIG_RESET_PD_VMIF(a) (a & (~(MSD_SIF_LMEM_CONFIG_PD_MASK << MSD_SIF_LMEM_CONFIG_PD_VMIF_POS )))
|
||||
|
||||
|
||||
|
||||
// Row-store buffer control
|
||||
//--------------------------
|
||||
// MSD_SIF_RSB_CTRL_STAT_ADDR (0x6e) //0x1b8
|
||||
#define MSD_SIF_RSB_SWITCH_REGION_ACCESS_POS 0x0
|
||||
#define MSD_SIF_RSB_SWITCH_REGION_ACCESS_MASK 0x1
|
||||
#define MSD_SIF_RSB_SWITCH_REGION_ACCESS_GET(r) (( r >> MSD_SIF_RSB_SWITCH_REGION_ACCESS_POS ) & MSD_SIF_RSB_SWITCH_REGION_ACCESS_MASK )
|
||||
#define MSD_SIF_RSB_SWITCH_REGION_ACCESS_SET(w) (( w & MSD_SIF_RSB_SWITCH_REGION_ACCESS_MASK ) << MSD_SIF_RSB_SWITCH_REGION_ACCESS_POS )
|
||||
#define MSD_SIF_RSB_INT_BASE_ADDR_SET(a) ((0x1fff & a)<<0) // 12:0
|
||||
#define MSD_SIF_RSB_XFR_XNUM_MASK ((0xff )<<13)
|
||||
#define MSD_SIF_RSB_XFR_XNUM_SET(a) ((0xff & a )<<13) //20:13
|
||||
#define MSD_SIF_RSB_XFR_YNUM_MASK ((0x7 )<<21) // 23:21
|
||||
#define MSD_SIF_RSB_XFR_YNUM_SET(a) ((0x7 & a)<<21) // 23:21
|
||||
#define MSD_SIF_RSB_SPLIT_FACTOR_MASK ((0x3 )<<24) //25:24
|
||||
#define MSD_SIF_RSB_SPLIT_FACTOR_SET(a) ((0x3 & a)<<24) //25:24
|
||||
#define MSD_SIF_RSB_XFR_MODE_MASK ((0x3 )<<26) //27:26
|
||||
#define MSD_SIF_RSB_XFR_MODE_SET(a) ((0x3 & a)<<26) //27:26
|
||||
#define MSD_SIF_RSB_XFR_START_MASK ((0x1 )<<28) //28
|
||||
#define MSD_SIF_RSB_XFR_START_SET(a) ((0x1 & a)<<28) //28
|
||||
#define MSD_SIF_RSB_APB_ACC_EN_MASK ((0x1 )<<31) //31
|
||||
#define MSD_SIF_RSB_APB_ACC_EN_SET(a) ((0x1 & a)<<31) //31
|
||||
|
||||
#define MSD_SIF_RSB_XFR_PROG_GET(a) (( a >>29) & 0x1) //29
|
||||
#define MSD_SIF_RSB_XFR_DONE_GET(a) (( a >>30) & 0x1) //30
|
||||
#define MSD_SIF_RSB_XFR_MODE_GET(a) (( a >>26) & 0x3) //27:26
|
||||
|
||||
|
||||
// Ancillary RSB transfer defines
|
||||
//-------------------------------
|
||||
#define MSD_SIF_RSB_INT_BASE_ADDR_MASK 0x1FFFF
|
||||
|
||||
//MSD_SIF_EXT_RSB_BASE_ADDR (0X6f) //0x1bc
|
||||
#define MSD_SIF_EXT_RSB_BASE_ADDR_SET(a) (a & 0xffffff) // 31:3
|
||||
//MSD_SIF_EXT_XFR_PARAMS_ADDR (0x70) 0x1c0
|
||||
#define MSD_SIF_EXT_XFR_PARAM_TF_TYPE_MASK ((0x3) <<30 ) //31:30 0:2DLU; 1:2DCR 2:MINF 3:1DTF ;
|
||||
#define MSD_SIF_EXT_XFR_PARAM_TF_TYPE(a) ((a & 0x3) <<30 ) //31:30 0:2DLU; 1:2DCR 2:MINF 3:1DTF ;
|
||||
#define MSD_SIF_EXT_XFR_PARAM_TYPE_GET(a) (( a >>30) & 0x3) //31:30
|
||||
// 2D transferred
|
||||
#define MSD_SIF_EXT_XFR_PARAM_FIELD_FRAME_MASK ((0x01)<<29) //29 : field 1 ; 0 frame
|
||||
#define MSD_SIF_EXT_XFR_PARAM_TOP_ROW_POS_MASK ((0x7ff)<<18) // row position in frame of top row of data in the transfer
|
||||
#define MSD_SIF_EXT_XFR_PARAM_COL_LFT_POS_MASK ((0xff )<<10) // collumn position in frame of left-most word in the transfer
|
||||
#define MSD_SIF_EXT_XFR_PARAM_NUM_ROW_MASK ((0x1f )<<5) // number of rows in a tile to be transferred
|
||||
#define MSD_SIF_EXT_XFR_PARAM_NUM_PER_ROW_MASK ((0x3) <<0) // number of words per row in a tile to be transferred
|
||||
|
||||
#define MSD_SIF_EXT_XFR_PARAM_FIELD_FRAME(a) ((a & 0x01)<<29) //29 : field 1 ; 0 frame
|
||||
#define MSD_SIF_EXT_XFR_PARAM_TOP_ROW_POS(a) ((a & 0x7ff)<<18) // row position in frame of top row of data in the transfer
|
||||
#define MSD_SIF_EXT_XFR_PARAM_COL_LFT_POS(a) ((a & 0xff )<<10) // collumn position in frame of left-most word in the transfer
|
||||
#define MSD_SIF_EXT_XFR_PARAM_NUM_ROW(a) ((a & 0x1f )<<5) // number of rows in a tile to be transferred
|
||||
#define MSD_SIF_EXT_XFR_PARAM_NUM_PER_ROW(a) ((a & 0x3) <<0) // number of words per row in a tile to be transferred
|
||||
// 1D transferred
|
||||
#define MSD_SIF_EXT_XFR_PARAM_NUM_WORDS_MASK ((0x1fff)<<0) // number of words to be transferred under 1D
|
||||
#define MSD_SIF_EXT_XFR_PARAM_NUM_WORDS(a) ((a & 0x1fff)<<0) // number of words to be transferred under 1D
|
||||
#define MSD_SIF_EXT_XFR_BASE_ADDR_SET(a) ( a & 0xffffff) // 31:3
|
||||
|
||||
#define MSD_SIF_PWT_BASE_ADDR_POS 0x0
|
||||
#define MSD_SIF_PWT_BASE_ADDR_MASK 0x3FFF
|
||||
#define MSD_SIF_PXD_BASE_ADDR_POS 0x10
|
||||
#define MSD_SIF_PXD_BASE_ADDR_MASK 0x3FFF
|
||||
|
||||
#define MSD_SIF_PUT_PWT_BASE(w) (( w & MSD_SIF_PWT_BASE_ADDR_MASK ) << MSD_SIF_PWT_BASE_ADDR_POS )
|
||||
#define MSD_SIF_PUT_PXD_BASE(w) (( w & MSD_SIF_PXD_BASE_ADDR_MASK ) << MSD_SIF_PXD_BASE_ADDR_POS )
|
||||
|
||||
#define MSD_SIF_BSD_BASE_ADDR_POS 0x0
|
||||
#define MSD_SIF_BSD_BASE_ADDR_MASK 0x3FFF
|
||||
#define MSD_SIF_DBFC_BASE_ADDR_POS 0x10
|
||||
#define MSD_SIF_DBFC_BASE_ADDR_MASK 0x3FFF
|
||||
#define MSD_SIF_RSB_USE_APB_OFF_POS 0x1F
|
||||
#define MSD_SIF_RSB_USE_APB_OFF_MASK 0x1
|
||||
|
||||
#define MSD_SIF_PUT_BSD_BASE(w) (( w & MSD_SIF_BSD_BASE_ADDR_MASK ) << MSD_SIF_BSD_BASE_ADDR_POS )
|
||||
#define MSD_SIF_PUT_DBFC_BASE(w) (( w & MSD_SIF_DBFC_BASE_ADDR_MASK ) << MSD_SIF_DBFC_BASE_ADDR_POS )
|
||||
#define MSD_SIF_PUT_RSB_USE_APB(w) (( w & MSD_SIF_RSB_USE_APB_OFF_MASK ) << MSD_SIF_RSB_USE_APB_OFF_POS )
|
||||
|
||||
#define MSD_SIF_MPRR_BASE_ADDR_POS 0x0
|
||||
#define MSD_SIF_MPRR_BASE_ADDR_MASK 0x3FFF
|
||||
#define MSD_SIF_MPRC_BASE_ADDR_POS 0x10
|
||||
#define MSD_SIF_MPRC_BASE_ADDR_MASK 0x3FFF
|
||||
|
||||
#define MSD_SIF_PUT_MPRR_BASE(w) (( w & MSD_SIF_MPRR_BASE_ADDR_MASK ) << MSD_SIF_MPRR_BASE_ADDR_POS )
|
||||
#define MSD_SIF_PUT_MPRC_BASE(w) (( w & MSD_SIF_MPRC_BASE_ADDR_MASK ) << MSD_SIF_MPRC_BASE_ADDR_POS )
|
||||
|
||||
|
||||
/* MVD VMIF Options */
|
||||
#define MSD_VMIF_TAG_ACK_ON_FLUSH_POS 0
|
||||
#define MSD_VMIF_MAX_RD_REQ_SIZE_POS 1
|
||||
#define MSD_VMIF_CACHE_ENAB_POS 3
|
||||
#define MSD_VMIF_CACHE_RST_STAT_POS 4
|
||||
#define MSD_VMIF_SPLIT_READS_POS 5
|
||||
#define MSD_VMIF_SPLIT_WRITES_POS 6
|
||||
#define MSD_VMIF_FS_OFFSET_8PIX_POS 7
|
||||
#define MSD_VMIF_FS_OFFSET_CHROMA_8PIX_POS 8
|
||||
#define MSD_VMIF_CACHE_16WAY_MODE_POS 9
|
||||
#define MSD_VMIF_SCALE_MODE_POS 10
|
||||
#define MSD_VMIF_RSB_EXT_CACHE_ENAB 11
|
||||
#define MSD_VMIF_MAX_RD_SIZE_CONFIG_POS 12
|
||||
#define MSD_VMIF_MBI_RD_BUS_ENAB_POS 13
|
||||
#define MSD_VMIF_CACHE_DIS_AUTO_RST_POS 15
|
||||
#define MSD_VMIF_MBI_WR_BUS_ENAB_POS 16
|
||||
|
||||
#define MSD_VMIF_DISABLE_BIT_POS 18
|
||||
#define MSD_VMIF_USE_RPR_STRIDES_POS 19
|
||||
#define MSD_VMIF_DBG_SEL_POS 20
|
||||
#define MSD_VMIF_USE_4K_CACHE_CTRL_POS 23
|
||||
#define MSD_VMIF_4K_CACHE_ENAB_POS 24
|
||||
#define MSD_VMIF_4K_CACHE_RST_STAT_POS 25
|
||||
#define MSD_VMIF_4K_CACHE_DIS_AUTO_RST_POS 26
|
||||
#define MSD_VMIF_PACK_FORMAT_POS 27
|
||||
#define MSD_VMIF_CACHE_MODE_POS 28
|
||||
#define MSD_VMIF_MPSAL_POS 30
|
||||
#define MSD_VMIF_CLR_FSBA_POS 31
|
||||
|
||||
/* Extension : MVD VMIF Options */
|
||||
/* With the introduction of Pixif some of thee bits have been re-used */
|
||||
#define MSD_VMIF_USE_FBC_RPR_MASK 0x08000000 /* Bit 27 */
|
||||
#define MSD_VMIF_USE_FBC_RPR_POS 27
|
||||
|
||||
#define MSD_VMIF_USE_MBI_RD_RPR_POS 13
|
||||
#define MSD_VMIF_USE_MBI_RD_CSC_POS 14
|
||||
#define MSD_VMIF_USE_MBI_RD_MASK 0x0006000 /* Bits 14: 13 */
|
||||
|
||||
#define MSD_VMIF_USE_MBI_WR_RPR_POS 23
|
||||
#define MSD_VMIF_USE_MBI_WR_CSC_POS 24
|
||||
#define MSD_VMIF_USE_MBI_WR_JPG_DBF_POS 25
|
||||
#define MSD_VMIF_USE_MBI_WR_MP2_VC1_POS 26
|
||||
#define MSD_VMIF_USE_MBI_WR_MASK 0x7800000 /* Bits 26: 23 */
|
||||
|
||||
#define MSD_VMIF_MAX_RD_128 0
|
||||
#define MSD_VMIF_MAX_RD_256 1
|
||||
#define MSD_VMIF_MAX_RD_512 2
|
||||
|
||||
/* MVD VMIF RSB ERT ARBITER CONTROL */
|
||||
|
||||
#define MSD_VMIF_RSB_CLIENT_DBF 0x0
|
||||
#define MSD_VMIF_RSB_CLIENT_MPR 0x1
|
||||
#define MSD_VMIF_RSB_CLIENT_PXD 0x2
|
||||
#define MSD_VMIF_RSB_CLIENT_BSD 0x3
|
||||
#define MSD_VMIF_RSB_CLIENT_PWT 0x4
|
||||
#define MSD_VMIF_RSB_CLIENT_HUF 0x5
|
||||
#define MSD_VMIF_RSB_CLIENT_MTL 0x6
|
||||
#define MSD_VMIF_RSB_CLIENT_APB 0x7
|
||||
#define MSD_VMIF_RSB_CLIENT_XFR 0x8
|
||||
#define MSD_VMIF_RSB_CLIENT_BBD 0x9
|
||||
#define MSD_VMIF_RSB_CLIENT_CQ 0xa
|
||||
#define MSD_VMIF_RSB_CLIENT_BOB 0xb
|
||||
#define MSD_VMIF_RSB_CLIENT_DFE 0xb /* Yes this is deliberately the same - they replace the other in certain core configs */
|
||||
#define MSD_VMIF_RSB_CLIENT_CQBE 0xc
|
||||
|
||||
#define MVD_RSB_ARB_CLIENT_MASK 0xFFFF
|
||||
#define MVD_RSB_ARB_READ_CLIENT_SHIFT 0x10
|
||||
|
||||
/* RSB Defines */
|
||||
|
||||
#define MSD_RSB_XFR_TYPE_LUMA 0x0
|
||||
#define MSD_RSB_XFR_TYPE_CHROMA 0x1
|
||||
#define MSD_RSB_XFR_TYPE_MBINFO 0x2
|
||||
#define MSD_RSB_XFR_TYPE_DATA 0x3
|
||||
|
||||
#define MSD_RSB_MODE_ONCHIP_TOEXT 0x0 // direct is chip to ext ; is chip transaction with ext ;
|
||||
#define MSD_RSB_MODE_OFFCHIP_TOEXT 0x1 // direct is OFF chip to ext ; is off RSB transaction with ext ; off RSB is usable ; on chip not used
|
||||
#define MSD_RSB_MODE_ONCHIP_FREXT 0x2 // direct is ext to chip ; is chip transaction with ext ;
|
||||
#define MSD_RSB_MODE_OFFCHIP_FREXT 0x3 // direct is ext to off RSB ; is off RSB transaction with ext ;off RSB is usable ; on chip not used
|
||||
#define MSD_RSB_APB_ACC_EN_BIT 0x80000000
|
||||
|
||||
|
||||
/* MSD RPR Defines */
|
||||
#define MSD_RPR_SIZE_WIDTH_POS 0
|
||||
#define MSD_RPR_SIZE_HEIGHT_POS 16
|
||||
#define MSD_RPR_SIZE_WIDTH_MASK 0x3fff //14 bits
|
||||
|
||||
#define MSD_RPR_FILL_VALUE_Y_POS 0
|
||||
#define MSD_RPR_FILL_VALUE_U_POS 8
|
||||
#define MSD_RPR_FILL_VALUE_V_POS 16
|
||||
#define MSD_RPR_FILL_VALUE_MASK 0xff // 8bits
|
||||
|
||||
#define MSD_RPR_CTRL_START_POS 0
|
||||
#define MSD_RPR_CTL_FILL_MODE_POS 1
|
||||
#define MSD_RPR_CTL_ROUNDING_POS 2
|
||||
#define MSD_RPR_CTL_H_PRIME_M_POS 8
|
||||
#define MSD_RPR_CTL_V_PRIME_N_POS 12
|
||||
#define MSD_RPR_CTL_PRIME_MASK 0xf
|
||||
#define MSD_RPR_CTL_IN_FS_IDC_POS 16
|
||||
#define MSD_RPR_CTL_OUT_FS_IDC_POS 24
|
||||
#define MSD_RPR_CTL_FS_IDC_MASK 0x1f
|
||||
|
||||
#define MSD_RPR_CTRL_START_BIT 1
|
||||
|
||||
#define MSD_RPR_STATUS_IN_PROG_POS 29
|
||||
|
||||
|
||||
/* Decoupled data packing */
|
||||
/* Pack Base Set */
|
||||
#define MSD_SIF_PLQ_PACK_ADDR_MASK 0xFFFFFFFF
|
||||
#define MSD_SIF_PLQ_PACK_ADDR_SHIFT 0x0
|
||||
|
||||
#define MSD_SIF_SET_PLQ_PACK_ADDR( w ) (( w & MSD_SIF_PLQ_WRPACK_ADDR_MASK ) << MSD_SIF_PLQ_WRPACK_ADDR_SHIFT )
|
||||
|
||||
/* PRB Bin configuration */
|
||||
#define MSD_SIF_PLQ_BIN_SIZE_MASK 0x3FFFFF
|
||||
#define MSD_SIF_PLQ_BIN_SIZE_SHIFT 0x0
|
||||
#define MSD_SIF_PLQ_NUM_BINS_MASK 0x3FF
|
||||
#define MSD_SIF_PLQ_NUM_BINS_SHIFT 0x16
|
||||
|
||||
#define MSD_SIF_SET_PLQ_BIN_SIZE( w ) (( w & MSD_SIF_PLQ_BIN_SIZE_MASK ) << MSD_SIF_PLQ_BIN_SIZE_SHIFT )
|
||||
#define MSD_SIF_SET_PLQ_NUM_BINS( w ) (( w & MSD_SIF_PLQ_NUM_BINS_MASK ) << MSD_SIF_PLQ_NUM_BINS_SHIFT )
|
||||
|
||||
/* DCP Bin configuration */
|
||||
#define MSD_SIF_DCP_START_BINDEX_MASK 0x3FF
|
||||
#define MSD_SIF_DCP_START_BINDEX_SHIFT 0x0
|
||||
#define MSD_SIF_DCP_NUM_BINS_MASK 0x3FF
|
||||
#define MSD_SIF_DCP_NUM_BINS_SHIFT 0xA
|
||||
|
||||
#define MSD_SIF_SET_DCP_START_BINDEX( w )(( w & MSD_SIF_DCP_START_BINDEX_MASK ) << MSD_SIF_DCP_START_BINDEX_SHIFT )
|
||||
#define MSD_SIF_SET_DCP_NUM_BINS( w ) (( w & MSD_SIF_DCP_NUM_BINS_MASK ) << MSD_SIF_DCP_NUM_BINS_SHIFT )
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Function Prototypes
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#endif /* _MVD_SIF_CONTROL_H_ */
|
||||
|
||||
/* End of file */
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Author : MediaIP FW Team
|
||||
File name : mvd_types.h
|
||||
Function : Used as a home for generic MVD base decoder
|
||||
types
|
||||
|
||||
***************************************************/
|
||||
|
||||
#ifndef _MVD_TYPES_H_
|
||||
#define _MVD_TYPES_H_
|
||||
|
||||
#include "basetype.h"
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// tAuxCRCData
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u_int32 uDpbCRC2;
|
||||
u_int32 uBSCRC;
|
||||
u_int32 uCRC0;
|
||||
u_int32 uCRC1;
|
||||
u_int32 uCRC2;
|
||||
u_int32 uCRC3;
|
||||
u_int32 uCRC4;
|
||||
u_int32 uCRC5;
|
||||
u_int32 uCRC6;
|
||||
u_int32 uCRC7;
|
||||
|
||||
} tAuxCRCData, *ptAuxCRCData;
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// tAuxCRC2Data
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u_int32 uCRC8;
|
||||
u_int32 uCRC9;
|
||||
u_int32 uCRC10;
|
||||
u_int32 uCRC11;
|
||||
u_int32 uCRC12;
|
||||
u_int32 uCRC13;
|
||||
u_int32 uCRC14;
|
||||
|
||||
} tAuxCRC2Data, *ptAuxCRC2Data;
|
||||
|
||||
#define MVD_TRUE 0x1UL
|
||||
#define MVD_FALSE 0x0UL
|
||||
|
||||
typedef float MvdFloat; // fVariableName, *pfPointerName
|
||||
typedef double MvdDouble; // dVariableName, *pdPointerName
|
||||
|
||||
typedef volatile u_int32 MvdHwReg; // rVariableName, *prPointerName
|
||||
typedef volatile u_int32 *MvdHwAddr;
|
||||
|
||||
/* ************** */
|
||||
/* Debug arrays */
|
||||
/* ************** */
|
||||
typedef struct
|
||||
{
|
||||
int32 index;
|
||||
int32 array[512];
|
||||
} DBG_ARRAY_512;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int32 index;
|
||||
int32 array[1024];
|
||||
} DBG_ARRAY_1024;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int32 index;
|
||||
int32 array[2048];
|
||||
} DBG_ARRAY_2048;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int32 index;
|
||||
int32 array[4096];
|
||||
} DBG_ARRAY_4096;
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// Metadata structs
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// TimeStamp Metadata
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u_int32 uPTS;
|
||||
u_int32 uDTS;
|
||||
u_int32 uPESFlags;
|
||||
bool bValid;
|
||||
|
||||
} tMVD_METADATA_TS, *ptMVD_METADATA_TS;
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// Pic Struct Metadata
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u_int32 uDummy;
|
||||
bool bValid;
|
||||
|
||||
} tMVD_METADATA_PIC_STRUCT, *ptMVD_METADATA_PIC_STRUCT;
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// UData Metadata
|
||||
|
||||
typedef struct
|
||||
{
|
||||
bool bValid;
|
||||
void * pUDataMemChunk;
|
||||
u_int32 uWrPtr;
|
||||
|
||||
} tMVD_METADATA_UDATA, *ptMVD_METADATA_UDATA;
|
||||
|
||||
#endif /* _MVD_TYPES_H_ */
|
||||
|
||||
/* End of file */
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Filename: DecoderLib.c
|
||||
Description: Decoder Library API level
|
||||
Author: Media IP FW team (Belfast & Shanghai)
|
||||
|
||||
****************************************************/
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "basetype.h"
|
||||
#include "mediaip_fw_types.h"
|
||||
#include "pal.h"
|
||||
#include "DecKernelLib.h"
|
||||
#include "DecKernelLibPrivate.h"
|
||||
#include "DecKernelLibCfg.h"
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Variables
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
DEC_KERNEL_LIB gDecKernelLib = { 0x0 };
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Code
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: decoder_kernel_lib_init //
|
||||
// //
|
||||
// DESCRIPTION: This function initialises the decoder library //
|
||||
// to be called from kernel space //
|
||||
// It's only purpose is to post interrupts via callback to a queue //
|
||||
// for processing in userspace //
|
||||
// //
|
||||
// INPUTS: pCfg - Pointer to a static configuration structure for the //
|
||||
// library //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: MEDIAIP_FW_STATUS_ //
|
||||
// OK - Success. //
|
||||
// ALREADY_INIT - This function has already been called and no //
|
||||
// subsequent call to decoderlib_term made //
|
||||
// //
|
||||
// NOTES: None. //
|
||||
// //
|
||||
// CONTEXT: This function must be called from non-interrupt context //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_FW_STATUS decoder_kernel_lib_init ( DECODERLIB_KERNEL_CFG * pCfg )
|
||||
{
|
||||
MEDIAIP_FW_STATUS eRetCode = MEDIAIP_FW_STATUS_OK;
|
||||
|
||||
if ( gDecKernelLib.bInit == FALSE )
|
||||
{
|
||||
gDecKernelLib.bInit = TRUE;
|
||||
|
||||
/* Make all necessary init calls */
|
||||
internal_decoder_kernel_lib_init ( pCfg );
|
||||
}
|
||||
else
|
||||
{
|
||||
eRetCode = MEDIAIP_FW_STATUS_ALREADY_INIT;
|
||||
}
|
||||
|
||||
return eRetCode;
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: decoderlib_register_event_callback //
|
||||
// //
|
||||
// DESCRIPTION: This function registers a handler for reporting decoder events //
|
||||
// //
|
||||
// INPUTS: hHandle - handle for the stream with which to register the //
|
||||
// callbacks //
|
||||
// pfCallback - Function ponter to be executed when a decoder //
|
||||
// event is raised //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: MEDIAIP_FW_STATUS_ //
|
||||
// OK - Success. //
|
||||
// BAD_HANDLE - hHandle is not a valid decoder library //
|
||||
// handle //
|
||||
// //
|
||||
// NOTES: None. //
|
||||
// //
|
||||
// CONTEXT: Unknown if there are any constraints here as yet //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_FW_STATUS decoder_kernel_lib_register_isr_callback ( u_int32 uMalIdx,
|
||||
DecKernelLib_Isr_Callback_t pfCallback )
|
||||
{
|
||||
|
||||
if ( gDecKernelLib.bInit == FALSE )
|
||||
{
|
||||
pal_trace( DECODER_TL_WARNING, "DECODER_LIB: decoder_kernel_lib_register_isr_callback : Invalid Malone\n", uMalIdx );
|
||||
|
||||
return MEDIAIP_FW_STATUS_BAD_HANDLE;
|
||||
}
|
||||
|
||||
internal_decoder_kernel_lib_register_isr_callback ( uMalIdx,
|
||||
pfCallback );
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: decoderlib_term //
|
||||
// //
|
||||
// DESCRIPTION: Deinitialises decode library //
|
||||
// //
|
||||
// INPUTS: None //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: MEDIAIP_FW_STATUS_ //
|
||||
// OK - Success. //
|
||||
// //
|
||||
// NOTES: None. //
|
||||
// //
|
||||
// CONTEXT: This function must be called from non-interrupt context //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_FW_STATUS decoder_kernel_lib_term ( )
|
||||
{
|
||||
MEDIAIP_FW_STATUS eRetCode = MEDIAIP_FW_STATUS_OK;
|
||||
|
||||
gDecKernelLib.bInit = FALSE;
|
||||
|
||||
return eRetCode;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Filename: DecLibCfg.h
|
||||
Description: Decoder Library Configuration
|
||||
Author: Media IP FW team (Belfast & Shanghai)
|
||||
|
||||
*******************************************************/
|
||||
|
||||
#ifndef _DECODER_LIB_CFG_H_
|
||||
#define _DECODER_LIB_CFG_H_
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
#include "video_subsystem.h"
|
||||
#endif
|
||||
#include "mediaip_fw_types.h"
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Macros
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/* Local defines cast to those in global cfg file */
|
||||
#define DECODERLIB_MAX_MALONES MEDIAIP_MAX_NUM_MALONES
|
||||
#define DECODERLIB_MAX_DBE_UNITS 0x2
|
||||
|
||||
/* These don't really need to be passed in the cfg methinks... */
|
||||
#define DECODERLIB_NUM_STREAMS NUM_DECODER_STREAMS
|
||||
#define DECODERLIB_MAX_NUM_FRAMES MAX_NUM_FRAMES_PER_STREAM
|
||||
#if HEVC_JVT_MODEL < 92
|
||||
#define DECODERLIB_MAX_MBI_FRAMES 0x12
|
||||
#else
|
||||
#define DECODERLIB_MAX_MBI_FRAMES 0x11
|
||||
#endif
|
||||
#define DECODERLIB_MAX_DFE_AREAS 0x1
|
||||
#define DECODERLIB_MAX_NUM_OVLP_FRMS 1
|
||||
#define DECODERLIB_METADATA_AREA_NULL 0xFF
|
||||
#define DECODERLIB_NUM_EVENTS_PER_STREAM 4
|
||||
#define DECODERLIB_NUM_CMDS_PER_STREAM 4
|
||||
|
||||
#define DECODERLIB_MAX_MVC_DPID 1
|
||||
#define DECODERLIB_MAX_MVC_TARGET_VIEWS 2
|
||||
#define DECODERLIB_MAX_MVC_VIEWS 4
|
||||
|
||||
#define DECODERLIB_MAX_DPVS 0x1
|
||||
#define DECODERLIB_PIXIF_MAX_UPIX_TARGETS 0x2
|
||||
#define DECODERLIB_PIXIF_MAX_FBC_TARGETS 0x2
|
||||
#define DECODERLIB_MAX_STREAM_LEVELS DECODERLIB_MAX_MVC_VIEWS
|
||||
|
||||
|
||||
#define DECODERLIB_MAX_STR_BUFFERS DECODERLIB_MAX_STREAM_LEVELS
|
||||
#define DECODERLIB_RC4_CONTEXT_VALS 66
|
||||
|
||||
#if ( TARGET_LEVEL == HAPS ) || ( TARGET_LEVEL == SIMULATION )
|
||||
#define DECODERLIB_NUM_DBG_FIFOS 26
|
||||
#else
|
||||
#define DECODERLIB_NUM_DBG_FIFOS 1
|
||||
#endif
|
||||
|
||||
#ifdef DECLIB_ENABLE_DCP
|
||||
#define DECODERLIB_MAX_CQ_PER_MALONE 0x3
|
||||
#else
|
||||
#define DECODERLIB_MAX_CQ_PER_MALONE 0x1
|
||||
#endif
|
||||
|
||||
// Enable processing of PAFF streams
|
||||
// If defined Field frame storage choice is made at a picture level
|
||||
// otherwise it is made as a sequence level
|
||||
//#define PIXIF_STORE_AS_PAFF
|
||||
|
||||
//-------------------------------------------------
|
||||
// Some options for testing different HW Configs
|
||||
//-------------------------------------------------
|
||||
//#define FSLCACHE0_BYPASS
|
||||
#define ALLOW_CHROMA_DP
|
||||
#define ALLOW_MPS_ALIGN
|
||||
#define ALLOW_OFFSET_FS
|
||||
//#define FORCE_UNCACHED_8x8
|
||||
//-------------------------------------------------
|
||||
|
||||
#endif /* _DECODER_LIB_CFG_H_ */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Filename: DecoderLibPrivate.c
|
||||
Description: Decoder Library API level
|
||||
Author: Kyle McAdoo - Media IP FW Team ( Belfast & Shanghai )
|
||||
|
||||
***************************************************/
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "basetype.h"
|
||||
#include "mediaip_fw_types.h"
|
||||
#include "pal.h"
|
||||
#include "DecKernelLibPrivate.h"
|
||||
#include "DecKernelLibHWControl.h"
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Variables
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
u_int32 uMvdKernelIrqPin[DECODERLIB_MAX_MALONES][0x2];
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Extern function prototypes
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
extern DEC_KERNEL_LIB gDecKernelLib;
|
||||
extern MALONE_KERNEL_HW_SESSION gMvdKernelHw[(DECODERLIB_MAX_MALONES + 1)];
|
||||
|
||||
extern MEDIAIP_IRQ_RETCODE mvd_kernel_hw_primary_isr ( u_int32 irq_val );
|
||||
extern MEDIAIP_IRQ_RETCODE mvd_kernel_hw_secondary_isr ( u_int32 irq_val );
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Code
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: internal_decoder_kernel_lib_init //
|
||||
// //
|
||||
// DESCRIPTION: This function initialises the decoder library //
|
||||
// more notes to follow when it works... //
|
||||
// //
|
||||
// INPUTS: None //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: MEDIAIP_FW_STATUS_ //
|
||||
// OK - Success. //
|
||||
// BAD_PARAMETER - Configuration structure not initialised //
|
||||
// ALREADY_INIT - //
|
||||
// //
|
||||
// NOTES: None. //
|
||||
// //
|
||||
// CONTEXT: This function must be called from non-interrupt context //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_FW_STATUS internal_decoder_kernel_lib_init ( DECODERLIB_KERNEL_CFG * pCfg )
|
||||
{
|
||||
MEDIAIP_FW_STATUS RetCode = MEDIAIP_FW_STATUS_OK;
|
||||
|
||||
/* Parse interrupt config */
|
||||
internal_decoder_kernel_lib_parse_cfg ( pCfg,
|
||||
FALSE );
|
||||
|
||||
/* Setup hardware view of Malone */
|
||||
mvd_kernel_hw_control_init ( pCfg );
|
||||
|
||||
return RetCode;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: internal_decoder_kernel_lib_register_isr_callback //
|
||||
// //
|
||||
// DESCRIPTION: This function registers handlers for event processing //
|
||||
// more notes to follow when it works... //
|
||||
// //
|
||||
// INPUTS: hHandle - handle for the stream with which to register the //
|
||||
// callbacks //
|
||||
// pfCallback - Function ponter to be executed when a decoder //
|
||||
// event is raised //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: None. //
|
||||
// //
|
||||
// NOTES: None. //
|
||||
// //
|
||||
// CONTEXT: Unknown if there are any constraints here as yet //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void internal_decoder_kernel_lib_register_isr_callback ( u_int32 uMalIdx,
|
||||
DecKernelLib_Isr_Callback_t pfCallback
|
||||
)
|
||||
{
|
||||
gDecKernelLib.pfCallback[uMalIdx] = pfCallback;
|
||||
}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: internal_decoder_kernel_lib_parse_cfg //
|
||||
// //
|
||||
// DESCRIPTION: Update DecoderLib structs with info from the configuration //
|
||||
// //
|
||||
// INPUTS: pCfg - The DecLib configuration //
|
||||
// bCheck - A control variable which allows prints on changes in //
|
||||
// //
|
||||
// OUTPUTS: None. //
|
||||
// //
|
||||
// RETURNS: None. //
|
||||
// //
|
||||
// NOTES: Set bCheck in snapshot restarts to see what may be different //
|
||||
// in the configuration of the generation and restart platforms //
|
||||
// //
|
||||
// CONTEXT: Call from thread context //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void internal_decoder_kernel_lib_parse_cfg ( DECODERLIB_KERNEL_CFG * pCfg,
|
||||
bool bCheck
|
||||
)
|
||||
{
|
||||
PAL_PFNISR pFnDecodeIsr;
|
||||
u_int32 uMalIdx;
|
||||
|
||||
gDecKernelLib.uNumMalones = pCfg->uNumMalones;
|
||||
|
||||
for ( uMalIdx = 0x0; uMalIdx < gDecKernelLib.uNumMalones; uMalIdx++ )
|
||||
{
|
||||
uMvdKernelIrqPin[uMalIdx][0x0] = pCfg->uMaloneIrqPin[uMalIdx][0x0];
|
||||
uMvdKernelIrqPin[uMalIdx][0x1] = pCfg->uMaloneIrqPin[uMalIdx][0x1];
|
||||
}
|
||||
|
||||
/* Finally claim the interrupts */
|
||||
pFnDecodeIsr = ( PAL_PFNISR )mvd_kernel_hw_primary_isr;
|
||||
pal_int_register ( uMvdKernelIrqPin[0x0][0x0], pFnDecodeIsr, FALSE );
|
||||
pFnDecodeIsr = ( PAL_PFNISR )mvd_kernel_hw_secondary_isr;
|
||||
|
||||
/* This is a safety check in case a lazy player does not setup the second irq */
|
||||
if ( uMvdKernelIrqPin[0x0][0x0] != uMvdKernelIrqPin[0x0][0x1] )
|
||||
{
|
||||
pal_int_register ( uMvdKernelIrqPin[0x0][0x1], pFnDecodeIsr, FALSE );
|
||||
}
|
||||
|
||||
if ( gDecKernelLib.uNumMalones > 0x1 )
|
||||
{
|
||||
pFnDecodeIsr = ( PAL_PFNISR )mvd_kernel_hw_primary_isr;
|
||||
pal_int_register ( uMvdKernelIrqPin[0x1][0x0], pFnDecodeIsr, FALSE );
|
||||
pFnDecodeIsr = ( PAL_PFNISR )mvd_kernel_hw_secondary_isr;
|
||||
|
||||
if ( uMvdKernelIrqPin[0x1][0x0] != uMvdKernelIrqPin[0x1][0x1] )
|
||||
{
|
||||
pal_int_register ( uMvdKernelIrqPin[0x1][0x1], pFnDecodeIsr, FALSE );
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* End of file */
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Filename: DecKernelPrivate.h
|
||||
Description: Decoder Library Private header file - not
|
||||
for inclusion by code outside of decoder lib.
|
||||
Author: Media IP FW team (Belfast & Shanghai)
|
||||
|
||||
*******************************************************/
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "DecKernelLib.h"
|
||||
|
||||
/* Include NO other files here */
|
||||
|
||||
#ifndef _DECODER_KERN_LIB_PRIV_H_
|
||||
#define _DECODER_KERN_LIB_PRIV_H_
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Macros
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Global Structures
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// DecoderLib Context structure
|
||||
|
||||
typedef struct decoderlib_inst
|
||||
{
|
||||
bool bInit;
|
||||
u_int32 uNumMalones;
|
||||
/* One per Malone, kernel lib only has concept of Malone hardware, not */
|
||||
/* the individual streams running on it! */
|
||||
DecKernelLib_Isr_Callback_t pfCallback[DECODERLIB_MAX_MALONES];
|
||||
|
||||
} DEC_KERNEL_LIB;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Function Prototypes
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_FW_STATUS internal_decoder_kernel_lib_init ( DECODERLIB_KERNEL_CFG * pCfg );
|
||||
|
||||
void internal_decoder_kernel_lib_register_isr_callback ( u_int32 uMalIdx,
|
||||
DecKernelLib_Isr_Callback_t pfCallback
|
||||
);
|
||||
|
||||
void internal_decoder_kernel_lib_parse_cfg ( DECODERLIB_KERNEL_CFG * pCfg,
|
||||
bool bCheck
|
||||
);
|
||||
|
||||
#endif /* _DECODER_KERN_LIB_PRIV_H_ */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,343 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
Filename: basetype.h
|
||||
Description: Public header file for use in all FW
|
||||
Author: Media IP FW team (Belfast)
|
||||
|
||||
************************************************/
|
||||
|
||||
#ifndef _BASETYPE_H_
|
||||
#define _BASETYPE_H_
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#else
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#endif
|
||||
|
||||
#ifdef WIN32
|
||||
#if _MSC_VER
|
||||
typedef unsigned __int64 u_int64;
|
||||
#else
|
||||
typedef unsigned long long u_int64;
|
||||
#endif
|
||||
#else
|
||||
typedef unsigned long long u_int64;
|
||||
#endif
|
||||
|
||||
#ifdef MALONE_64BIT_ADDR
|
||||
typedef uint64_t uint_addr;
|
||||
#else
|
||||
typedef uint32_t uint_addr;
|
||||
#endif
|
||||
|
||||
typedef uint32_t u_int32;
|
||||
typedef uint16_t u_int16;
|
||||
typedef uint8_t u_int8;
|
||||
|
||||
//Alignment Macro
|
||||
#define ALIGN_SIZE(x) (((x)+sizeof(u_int32) - 1)/(sizeof(u_int32)))
|
||||
|
||||
#ifdef WIN32
|
||||
#if _MSC_VER
|
||||
typedef signed __int64 int64;
|
||||
#else
|
||||
typedef signed long long int64;
|
||||
#endif
|
||||
#else
|
||||
typedef signed long long int64;
|
||||
#endif
|
||||
|
||||
typedef int32_t int32;
|
||||
typedef int16_t int16;
|
||||
typedef int8_t int8;
|
||||
typedef unsigned char BYTE;
|
||||
|
||||
// XXX:TAS No idea what all this ifdefing is about
|
||||
// should just need the C++ ifdef
|
||||
#ifndef HOST_BUILD
|
||||
#ifndef COREPLAY_API
|
||||
#ifndef _MSC_VER
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
typedef unsigned int bool;
|
||||
#endif
|
||||
#endif
|
||||
#else
|
||||
#ifndef _MSC_VER
|
||||
typedef unsigned int bool;
|
||||
#endif
|
||||
#endif
|
||||
#else
|
||||
#ifndef __cplusplus
|
||||
// bool is defined in cpp
|
||||
typedef unsigned int bool;
|
||||
#endif /* __cplusplus */
|
||||
#endif
|
||||
|
||||
typedef unsigned char BOOLEAN;
|
||||
|
||||
#define VOID_PARAMS void
|
||||
|
||||
#define INT32 int32
|
||||
|
||||
#define UINT8 u_int8
|
||||
#define UINT16 u_int16
|
||||
#define UINT32 u_int32
|
||||
#define UINT64 u_int64
|
||||
#ifdef _MSC_VER
|
||||
#define BOOL int
|
||||
#else
|
||||
#define BOOL bool
|
||||
#endif
|
||||
#define SINT8 int8
|
||||
#define SINT16 int16
|
||||
#define SINT32 int32
|
||||
#ifdef WIN32
|
||||
#define SINT64 int64
|
||||
#define SINT64_MIN (-9223372036854775807i64 - 1i64)
|
||||
#else
|
||||
#define SINT64 int64
|
||||
#define SINT64_MIN (-9223372036854775807LL - 1LL)
|
||||
#endif
|
||||
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
#define SUCCESS 0
|
||||
#define FAILURE -1
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#else // 'C'
|
||||
#ifndef false
|
||||
#define false 0
|
||||
#endif
|
||||
#ifndef true
|
||||
#define true 1
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#ifndef OKAY
|
||||
#define OKAY 0
|
||||
#endif
|
||||
|
||||
#ifndef ZERO
|
||||
#define ZERO 0
|
||||
#endif
|
||||
|
||||
// Define more error types as used - 1st is generic
|
||||
#define MEDIAIP_ERROR_FLAG 1
|
||||
#define MEDIAIP_END_ES 2
|
||||
#define MEDIAIP_DECODER_EXIT 3
|
||||
#define MEDIAIP_ENCODER_EXIT 4
|
||||
#define MEDIAIP_VC1D_NOFREEFRAMES 5
|
||||
#define MEDIAIP_DECODER_SKIP 6
|
||||
|
||||
/* Alignment macros - align address to a specific byte alignment */
|
||||
#define MEDIAIP_ALIGN_16(addr) addr = (addr + (( 0x1 << 0x4 ) - 0x1 ) ) & ~((( 0x1 << 0x4 ) - 0x1 ))
|
||||
#define MEDIAIP_ALIGN_32(addr) addr = (addr + (( 0x1 << 0x5 ) - 0x1 ) ) & ~((( 0x1 << 0x5 ) - 0x1 ))
|
||||
#define MEDIAIP_ALIGN_64(addr) addr = (addr + (( 0x1 << 0x6 ) - 0x1 ) ) & ~((( 0x1 << 0x6 ) - 0x1 ))
|
||||
#define MEDIAIP_ALIGN_128(addr) addr = (addr + (( 0x1 << 0x7 ) - 0x1 ) ) & ~((( 0x1 << 0x7 ) - 0x1 ))
|
||||
#define MEDIAIP_ALIGN_256(addr) addr = (addr + (( 0x1 << 0x8 ) - 0x1 ) ) & ~((( 0x1 << 0x8 ) - 0x1 ))
|
||||
#define MEDIAIP_ALIGN_512(addr) addr = (addr + (( 0x1 << 0x9 ) - 0x1 ) ) & ~((( 0x1 << 0x9 ) - 0x1 ))
|
||||
|
||||
/* used when declaring single bitfields
|
||||
*/
|
||||
#define FLAG 1
|
||||
|
||||
#ifndef WIN32
|
||||
#if CPU == MIPS
|
||||
#define DOUBLE_ALIGN __attribute__((aligned(8)))
|
||||
#define SECTION(sec) __attribute__ ((section (#sec)))
|
||||
#define ALIGNED(ali) __attribute__ ((aligned (ali)))
|
||||
#else
|
||||
#define DOUBLE_ALIGN
|
||||
#endif
|
||||
#endif // win32
|
||||
/* We need to stop defining ARM and use only CPU == ARM !!! */
|
||||
/* Lose all #ifdef ARM from code */
|
||||
|
||||
/* - Only for RCVCT */
|
||||
#ifdef __CC_ARM
|
||||
#define ALIGN_8_u_int8 __align(8) u_int8
|
||||
#define ALIGN_8_u_int16 __align(8) u_int16
|
||||
#define ALIGN_8_u_int32 __align(8) u_int32
|
||||
#define ALIGN_256_u_int16 __align(256) u_int16
|
||||
#define ALIGN_256_u_int32 __align(256) u_int32
|
||||
#define ALIGN_1024_u_int32 __align(1024) u_int32
|
||||
#define ALIGN_1024_u_int64 __align(1024) u_int64
|
||||
#define ALIGN_1024 __align(1024)
|
||||
#else
|
||||
/* All others? */
|
||||
#define ALIGN_8_u_int8 u_int8 __attribute__((aligned(8)))
|
||||
#define ALIGN_8_u_int16 u_int16 __attribute__((aligned(8)))
|
||||
#define ALIGN_8_u_int32 u_int32 __attribute__((aligned(8)))
|
||||
#define ALIGN_256_u_int16 u_int16 __attribute__((aligned(256)))
|
||||
#define ALIGN_256_u_int32 u_int32 __attribute__((aligned(256)))
|
||||
#define ALIGN_1024_u_int32 u_int32 __attribute__((aligned(1024)))
|
||||
#define ALIGN_1024_u_int64 u_int64 __attribute__((aligned(1024)))
|
||||
#define ALIGN_1024 __attribute__((aligned(1024)))
|
||||
#endif
|
||||
|
||||
#ifndef COREPLAY_API
|
||||
#if RTOS == UCOS
|
||||
|
||||
/* Additions for uCOS */
|
||||
|
||||
typedef unsigned char INT8U; /* Unsigned 8 bit quantity */
|
||||
typedef signed char INT8S; /* Signed 8 bit quantity */
|
||||
typedef unsigned int INT16U; /* Unsigned 16 bit quantity */
|
||||
typedef signed int INT16S; /* Signed 16 bit quantity */
|
||||
typedef unsigned long INT32U; /* Unsigned 32 bit quantity */
|
||||
typedef signed long INT32S; /* Signed 32 bit quantity */
|
||||
typedef float FP32; /* Single precision floating point */
|
||||
typedef double FP64; /* Double precision floating point */
|
||||
|
||||
typedef unsigned int OS_STK; /* Each stack entry is 16-bit wide */
|
||||
typedef unsigned int OS_CPU_SR; /* Define size of CPU status register (PSR = 32 bits) */
|
||||
|
||||
#define UBYTE INT8U /* ... to uC/OS V1.xx. Not actually needed for ... */
|
||||
#define WORD INT16S /* ... uC/OS-II. */
|
||||
#define UWORD INT16U
|
||||
#define LONG INT32S
|
||||
#define ULONG INT32U
|
||||
|
||||
#endif
|
||||
|
||||
typedef signed short int SHORT; /* Signed 16 bit quantity */
|
||||
typedef unsigned short USHORT;
|
||||
|
||||
#endif /* COREPLAY_API */
|
||||
|
||||
/****************************************************************************/
|
||||
/* */
|
||||
/* Hardware register access macros */
|
||||
/* */
|
||||
/****************************************************************************/
|
||||
|
||||
#define RMO(y) \
|
||||
( ((y) & 0x00000001) ? 0 : \
|
||||
( ((y) & 0x00000002) ? 1 : \
|
||||
( ((y) & 0x00000004) ? 2 : \
|
||||
( ((y) & 0x00000008) ? 3 : \
|
||||
( ((y) & 0x00000010) ? 4 : \
|
||||
( ((y) & 0x00000020) ? 5 : \
|
||||
( ((y) & 0x00000040) ? 6 : \
|
||||
( ((y) & 0x00000080) ? 7 : \
|
||||
( ((y) & 0x00000100) ? 8 : \
|
||||
( ((y) & 0x00000200) ? 9 : \
|
||||
( ((y) & 0x00000400) ? 10 : \
|
||||
( ((y) & 0x00000800) ? 11 : \
|
||||
( ((y) & 0x00001000) ? 12 : \
|
||||
( ((y) & 0x00002000) ? 13 : \
|
||||
( ((y) & 0x00004000) ? 14 : \
|
||||
( ((y) & 0x00008000) ? 15 : \
|
||||
( ((y) & 0x00010000) ? 16 : \
|
||||
( ((y) & 0x00020000) ? 17 : \
|
||||
( ((y) & 0x00040000) ? 18 : \
|
||||
( ((y) & 0x00080000) ? 19 : \
|
||||
( ((y) & 0x00100000) ? 20 : \
|
||||
( ((y) & 0x00200000) ? 21 : \
|
||||
( ((y) & 0x00400000) ? 22 : \
|
||||
( ((y) & 0x00800000) ? 23 : \
|
||||
( ((y) & 0x01000000) ? 24 : \
|
||||
( ((y) & 0x02000000) ? 25 : \
|
||||
( ((y) & 0x04000000) ? 26 : \
|
||||
( ((y) & 0x08000000) ? 27 : \
|
||||
( ((y) & 0x10000000) ? 28 : \
|
||||
( ((y) & 0x20000000) ? 29 : \
|
||||
( ((y) & 0x40000000) ? 30 : \
|
||||
( ((y) & 0x80000000) ? 31 : 0 ))))))))))))))))))))))))))))))))
|
||||
|
||||
/*
|
||||
* Access macros used to get, set/clear bits within a hardware register.
|
||||
* These macros *do not* perform any automatic shifting of bits and are
|
||||
* meant to be used with bit definitions which include their encoded bit
|
||||
* position within the register definition (e.g. an enable bit).
|
||||
*/
|
||||
|
||||
#ifdef VSIM_ENV
|
||||
UINT32 MEDIAIP_GET(UINT32,UINT32);
|
||||
void MEDIAIP_SET(UINT32,UINT32,UINT32);
|
||||
#define MEDIAIP_PUT(reg,mask,val) { \
|
||||
VSimAPI_WriteRegister((UINT32) reg, val); \
|
||||
}
|
||||
UINT32 MEDIAIP_SM_GET(volatile UINT32 *);
|
||||
void MEDIAIP_SM_SET(volatile UINT32 *, UINT32, UINT32 );
|
||||
void MEDIAIP_SM_PUT(volatile UINT32 *, UINT32 );
|
||||
|
||||
#else
|
||||
|
||||
#define MEDIAIP_GET(reg,mask) (*(LPREG)(reg) & (mask))
|
||||
#define MEDIAIP_SET(reg,mask,val) (*(LPREG)(reg)) = ((*(LPREG)(reg) & ~(mask)) | ((val) & (mask)))
|
||||
#define MEDIAIP_PUT(reg,val) (*(LPREG)(reg)) = (val)
|
||||
#define MEDIAIP_SM_GET(x) (*(x))
|
||||
#define MEDIAIP_SM_SET(a,b,c) (*(a)) = (((*(a)) & ~(b)) | ((c) & (b)))
|
||||
#define MEDIAIP_SM_PUT(a,b) (*(a)) = (b)
|
||||
|
||||
// IDJ: Consider using this?
|
||||
// No- there are only a few instances where this would make a difference.
|
||||
//efine MEDIAIP_SET(reg,mask,val) (*(LPREG)(reg)) = ((~(mask) ? 0 : (*(LPREG)(reg) & ~(mask))) | ((val) & (mask)))
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Access macros used to get & set a numerical value within a hardware
|
||||
* register. These macros perform automatic shifting (based on the mask)
|
||||
* of the numerical value used. These macros are useful for setting a
|
||||
* numerical value into a multi-bit contiguous field within a register.
|
||||
*/
|
||||
#define MEDIAIP_GET_VAL(reg,mask) ((*(LPREG)(reg) & (mask)) >> RMO(mask))
|
||||
#define MEDIAIP_SET_VAL(reg,mask,val) (*(LPREG)(reg)) = \
|
||||
((*(LPREG)(reg) & ~(mask)) | (((unsigned long)(val) << RMO(mask)) & (mask)))
|
||||
|
||||
#define MEDIAIP_REGWRITE(reg,val) *((LPREG)(reg)) = (val)
|
||||
#define MEDIAIP_REGREAD(reg) *((LPREG)(reg))
|
||||
|
||||
|
||||
#define MEDIAIP_SET_REG(reg,mask,val) reg = ((reg & ~(mask)) | ((val) & (mask)))
|
||||
#define MEDIAIP_GET_REG(reg,mask) reg & mask
|
||||
|
||||
typedef unsigned long HW_DWORD; /* was u_int32; */
|
||||
typedef unsigned short HW_WORD; /* was u_int16; */
|
||||
typedef unsigned char HW_BYTE; /* was u_int8; */
|
||||
typedef unsigned int HW_BOOL; /* was bool; */
|
||||
typedef void HW_VOID;
|
||||
|
||||
typedef volatile u_int32 *LPREG;
|
||||
|
||||
#ifdef __CC_ARM
|
||||
#define FUNC_INLINE __inline
|
||||
#else
|
||||
#define FUNC_INLINE inline
|
||||
#endif
|
||||
|
||||
#endif /* _BASETYPE_H_ */
|
||||
|
||||
/* End of File */
|
||||
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Filename: mediaip_fw_defines.h
|
||||
Description: Contains general definitions for
|
||||
module based architecture
|
||||
Author: Media IP FW team - Belfast
|
||||
|
||||
TODO-KMC - Should remove this file!!
|
||||
**************************************************/
|
||||
|
||||
#ifndef _MEDIAIP_FW_DEFINES_H_
|
||||
#define _MEDIAIP_FW_DEFINES_H_
|
||||
|
||||
/* In use MACROS for use by types shared across modules */
|
||||
/* When adding new modules, endeavour to maintain the same 'position' as that suggested by the */
|
||||
/* module's position in the MEDIAIP_FW_HANDLE_TYPE enumeration - see Modules/Public/handle.h */
|
||||
|
||||
#define IN_USE_DECODER ( 1 << 0x0 )
|
||||
#define IN_USE_ENCODER ( 1 << 0x1 )
|
||||
#define IN_USE_IMG_PORT ( 1 << 0x2 )
|
||||
#define IN_USE_DISPLAY ( 1 << 0x3 )
|
||||
#define IN_USE_VAMUX ( 1 << 0x4 )
|
||||
#define IN_USE_VIPP ( 1 << 0x5 )
|
||||
#define IN_USE_SYS_API ( 1 << 0x10 )
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// Frame Store Display Data make-up
|
||||
|
||||
// Read
|
||||
#define FRAME_STORE_DISP_DATA_FSID(r) ((r>>0)&0x3f)
|
||||
#define FRAME_STORE_DISP_DATA_RPT_FIRST_FLD(r) ((r>>15)&0x1) // IDJ: Pass RFF (borrow a bit from unused base addr field)
|
||||
#define FRAME_STORE_DISP_DATA_SPS_IDC_BITS(r) ((r>>16)&0x7)
|
||||
#define FRAME_STORE_DISP_DATA_DANG_FIELD_BIT(r) ((r>>19)&0x1)
|
||||
#define FRAME_STORE_DISP_DATA_FIELD_MODE_BIT(r) ((r>>20)&0x1)
|
||||
#define FRAME_STORE_DISP_DATA_BOT_FIRST_BIT(r) ((r>>21)&0x1)
|
||||
#define FRAME_STORE_DISP_DATA_SKIP_PIC_BITS(r) ((r>>22)&0x3)
|
||||
#define FRAME_STORE_DISP_DATA_SYS_DATA_BITS(r) ((r>>24)&0xFF)
|
||||
#define FRAME_STORE_DISP_DATA_FRAME_BADDR(r) ((r>>0)&0x7FFF)
|
||||
#define FRAME_STORE_DATAFIELDS(a) (a&0xffff8000) // IDJ - bit 15 used above
|
||||
|
||||
// Write
|
||||
#define FRAME_STORE_DISP_DATA_PUT_FSID(a) ((a&0x3f) << 0)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_FRAME_BADDR(a) ((a&0x7fff) << 0)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_DUPLC_FRAME_SENT(a) ((a&0x1) << 14) // RayC/JKD: but used to control when duplicate frames are sent
|
||||
#define FRAME_STORE_DISP_DATA_PUT_DUPLC_FRAME_SENT_GET(a) ((a>>14)&0x1)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_RPT_FIRST_FIELD(a) ((a&0x1) << 15) // IDJ Borrow a bit from BADDR field (not used)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_DISP_PARAM_ID(a) ((a&0x7) << 16)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_DANGLING_FIELD(a) ((a&0x1) << 19)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_FIELD_MODE(a) ((a&0x1) << 20)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_BOT_FIELD_FIRST(a) ((a&0x1) << 21)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_TOP_SKIPPED(a) ((a&0x1) << 22)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_BOT_SKIPPED(a) ((a&0x1) << 23)
|
||||
#define FRAME_STORE_DISP_DATA_PUT_SYS_DATA(a) ((a&0xff) << 24)
|
||||
|
||||
#define NUM_DISP_PUSHES_MASK 0xFF00
|
||||
#define NUM_DISP_PUSHES_POS 8
|
||||
#define NUM_DISP_PUSHES_SET(x) (x<<NUM_DISP_PUSHES_POS)
|
||||
#define NUM_DISP_PUSHES_GET(x) ( (x&NUM_DISP_PUSHES_MASK) >> NUM_DISP_PUSHES_POS)
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// Display Params
|
||||
|
||||
#define DISP_INFO_USER_DATA_ATTACHED_MASK 0x1
|
||||
#define DISP_INFO_USER_DATA_ATTACHED_POS 0
|
||||
#define DISP_INFO_GET_USER_DATA_ATTACHED(x) ((x&DISP_INFO_USER_DATA_ATTACHED_MASK)>>DISP_INFO_USER_DATA_ATTACHED_POS)
|
||||
#define DISP_INFO_USER_DATA_MASK 0xFFFF
|
||||
#define DISP_INFO_USER_DATA_POS 16
|
||||
#define DISP_INFO_GET_USER_DATA(x) ((x>>DISP_INFO_USER_DATA_POS)&DISP_INFO_USER_DATA_MASK)
|
||||
|
||||
// uScanFormat defines
|
||||
|
||||
#define DISP_SCAN_FORMAT_INTERLACED 0x0
|
||||
#define DISP_SCAN_FORMAT_PROGRESSIVE 0x1
|
||||
#define DISP_SCAN_FORMAT_VALID_GET(r) (r&0x1)
|
||||
#define DISP_SCAN_FORMAT_GET(r) ((r&0x2)>>1)
|
||||
#define DISP_SCAN_FORMAT_VALID_SET(r) ((r&0x1)<<0)
|
||||
#define DISP_SCAN_FORMAT_SET(r) ((r&0x1)<<1)
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// General defines - base on Stream descriptor for Pecos
|
||||
|
||||
#define STOP_IMMEDIATE 0x0
|
||||
#define STOP_COMPLETE_DISPLAY 0x1
|
||||
|
||||
#define FORMAT_VC1 0x2
|
||||
#define FORMAT_MPEG2 0x1
|
||||
#define FORMAT_MPEG4 0x0
|
||||
#define FORMAT_MPEG2_DBEN 0x1
|
||||
#define FORMAT_MPEG2_DBDRNGEN 0x2
|
||||
|
||||
#define STREAM_MODE_ES 0x1
|
||||
#define STREAM_MODE_PES 0x0
|
||||
|
||||
#define DELIVERY_MODE_TSP_DIRECT 0x0
|
||||
#define DELIVERY_MODE_BSP 0x1
|
||||
#define DELIVERY_MODE_BSDMA 0x2
|
||||
|
||||
// Buffer Indices
|
||||
#define SD_BUFIND_ESBUF_MASK 0xFF
|
||||
#define SD_BUFIND_ESBUF_SHIFT 0
|
||||
#define SD_BUFIND_STC_MASK 0x30000
|
||||
#define SD_BUFIND_STC_SHIFT 16
|
||||
#define SD_BUFIND_ESBUF_GET(x) ((x&SD_BUFIND_ESBUF_MASK)>>SD_BUFIND_ESBUF_SHIFT)
|
||||
#define SD_BUFIND_STC_GET(x) ((x&SD_BUFIND_STC_MASK)>>SD_BUFIND_STC_SHIFT)
|
||||
|
||||
#define UD_ORDER_DECODE 0x1
|
||||
#define UD_ORDER_DISPLAY 0x2
|
||||
#define UD_ORDER_DECODEANDDISPLAY 0x3
|
||||
|
||||
#define PRINT_UART4(a,b,c,d)
|
||||
#define PRINT_UART5(a,b,c,d,e)
|
||||
|
||||
#define DISPLAY_ASPECT_RATIO_4_3 0x2
|
||||
#define DISPLAY_ASPECT_RATIO_16_9 0x3
|
||||
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// PTS capture descriptor flags
|
||||
#define PTS_DESCRIPTOR_PTS_LO 0x00000000
|
||||
#define PTS_DESCRIPTOR_DTS_LO 0x00000004
|
||||
#define PTS_DESCRIPTOR_FLAGS 0x00000008
|
||||
#define PTS_DESCRIPTOR_WRAP_COUNT 0x00000009
|
||||
#define PTS_DESCRIPTOR_TIMEBASE_ID 0x0000000A
|
||||
#define PTS_DESCRIPTOR_MATURITY_ADDRESS 0x0000000C
|
||||
|
||||
#define PTS_DESCRIPTOR_FLAG_PTS_HI_MASK 0x00000001
|
||||
#define PTS_DESCRIPTOR_FLAG_PTS_HI_BIT 0
|
||||
#define PTS_DESCRIPTOR_FLAG_DTS_HI_MASK 0x00000002
|
||||
#define PTS_DESCRIPTOR_FLAG_DTS_HI_BIT 1
|
||||
#define PTS_DESCRIPTOR_FLAG_STC_PARITY_MASK 0x00000004
|
||||
#define PTS_DESCRIPTOR_FLAG_STC_PARITY_BIT 2
|
||||
#define PTS_DESCRIPTOR_FLAG_PENDING_MASK 0x00000008
|
||||
#define PTS_DESCRIPTOR_FLAG_PENDING_BIT 3
|
||||
#define PTS_DESCRIPTOR_FLAG_PESERROR_MASK 0x00000010
|
||||
#define PTS_DESCRIPTOR_FLAG_PESERROR_BIT 4
|
||||
|
||||
#define PTS_DESCRIPTOR_FLAG_ADDRESS_WRAP_COUNT_BIT 8
|
||||
#define PTS_DESCRIPTOR_FLAG_ADDRESS_WRAP_COUNT_MASK 0x0000FF00
|
||||
#define PTS_DESCRIPTOR_FLAG_TIMEBASE_ID_BIT 16
|
||||
#define PTS_DESCRIPTOR_FLAG_TIMEBASE_ID_MASK 0x000F0000
|
||||
#define PTS_DESCRIPTOR_FLAG_AVC_TAG_BIT 24
|
||||
#define PTS_DESCRIPTOR_FLAG_AVC_TAG_MASK 0xFF000000
|
||||
|
||||
// PTS debug descriptor extensions
|
||||
#define PTS_DESCRIPTOR_DEBUG 0x00000010
|
||||
#define PTS_DESCRIPTOR_DEBUG_PTS_DTS 0x00000010
|
||||
#define PTS_DESCRIPTOR_DEBUG_STC_SNAPSHOT 0x00000014
|
||||
#define PTS_DESCRIPTOR_DEBUG_DIFFERENCE 0x00000018
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAGS 0x0000001C
|
||||
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_NO_PTS 0x00000001
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_NO_STC 0x00000002
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_IS_DTS 0x00000004
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_RUNNING 0x00000008
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_INSANE 0x00000010
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_STC_B 0x00000020
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_STC_CURRENT 0x00000040
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_TIMEBASE_MISMATCH 0x00000080
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_LATE 0x00000100
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_EARLY 0x00000200
|
||||
#define PTS_DESCRIPTOR_DEBUG_FLAG_VERY_LATE 0x00000100
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// Tag descriptor defines
|
||||
// Flag definitions
|
||||
#define TAGLIST_SEI_PIC_STRUCT_FLAG_MASK 0x1
|
||||
#define TAGLIST_SEI_PIC_STRUCT_FLAG_SHIFT 0
|
||||
#define TAGLIST_SEI_FRAME_FREEZE_FLAG_MASK 0x2
|
||||
#define TAGLIST_SEI_FRAME_FREEZE_FLAG_SHIFT 1
|
||||
#define TAGLIST_SEI_FRAME_RELEASE_FLAG_MASK 0x4
|
||||
#define TAGLIST_SEI_FRAME_RELEASE_FLAG_SHIFT 2
|
||||
#define TAGLIST_SEI_SKIP_FLAG_MASK 0x8
|
||||
#define TAGLIST_SEI_SKIP_FLAG_SHIFT 3
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Frame status ~ TEMP
|
||||
#define FRAME_INUSE_BYIPP 0x1
|
||||
#define FRAME_FREE 0x0
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Scan format ~ TEMP
|
||||
#define SCAN_FORMAT_INTERLACED 0x0
|
||||
#define SCAN_FORMAT_PROGRESSIVE 0x1
|
||||
#define SCAN_FORMAT_VALID_GET(r) (r&0x1)
|
||||
#define SCAN_FORMAT_GET(r) ((r&0x2)>>1)
|
||||
#define SCAN_FORMAT_VALID_SET(r) ((r&0x1)<<0)
|
||||
#define SCAN_FORMAT_SET(r) ((r&0x1)<<1)
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Internal System Control Defines
|
||||
|
||||
#define NO_INTERNAL_CONTROL 0xFF
|
||||
#define SFD_INTERNAL_CONTROL 0x1
|
||||
#define AUTORECOVER_INTERNAL_CONTROL 0x2
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// SVC specific defines
|
||||
#define MEDIAIP_MAX_SVC_DID 0x3
|
||||
#define MEDIAIP_MAX_SVC_STR_BUFFERS 0x3
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Malone specific defines
|
||||
#define MEDIAIP_MAX_NUM_MALONES 0x2
|
||||
#define MEDIAIP_MAX_NUM_MALONE_IRQ_PINS 0x2
|
||||
|
||||
#define MEDIAIP_MAX_NUM_FSLCACHES 0x4
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Windsor specific defines
|
||||
#define MEDIAIP_MAX_NUM_WINDSORS 0x1
|
||||
#define MEDIAIP_MAX_NUM_WINDSOR_IRQ_PINS 0x2
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Subsystem specific defines
|
||||
#define MEDIAIP_MAX_NUM_IRQ_PINS 0x10
|
||||
#define MEDIAIP_MAX_NUM_CMD_IRQ_PINS 0x2
|
||||
#define MEDIAIP_MAX_NUM_MSG_IRQ_PINS 0x1
|
||||
#define MEDIAIP_MAX_NUM_TIMER_IRQ_PINS 0x4
|
||||
#define MEDIAIP_MAX_NUM_TIMER_IRQ_SLOTS 0x4
|
||||
|
||||
#define SUBSYSTEM_CFG_MAGIC_COOKIE 0xB0B1B2B3
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Max supported picture resolution, except H.264 and JPEG
|
||||
|
||||
#define MEDIAIP_MAX_PIC_WIDTH 2048
|
||||
#define MEDIAIP_MAX_PIC_HEIGHT 2048
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Encoder user data programming vals
|
||||
|
||||
#define MEDIAIP_ENC_USER_DATA_WORDS 16
|
||||
#define MEDIAIP_ENC_USER_DATA_BYTES ( MEDIAIP_ENC_USER_DATA_WORDS << 2 )
|
||||
|
||||
|
||||
|
||||
#endif /* _MEDIAIP_FW_DEFINES_H_ */
|
||||
|
||||
/* End of File */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,337 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
Filename : pal.h
|
||||
Description : Public header file for the
|
||||
Platform Abstraction Layer
|
||||
Author: Media IP FW team (Belfast)
|
||||
|
||||
***************************************************/
|
||||
|
||||
#ifndef _PAL_H_
|
||||
#define _PAL_H_
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header Files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
#include "stdio.h"
|
||||
#include "video_subsystem.h"
|
||||
#include "pal_os_al.h"
|
||||
/* For va_list */
|
||||
#include <stdarg.h>
|
||||
#endif
|
||||
#include "basetype.h"
|
||||
#include "pal_types.h"
|
||||
|
||||
#if ( TARGET_APP == VPU_TEST_APP )
|
||||
/* thread, semaphore and queue funcitons */
|
||||
#include "pal_linux_map.h"
|
||||
#endif
|
||||
|
||||
/* For buffer descriptor */
|
||||
#include "mediaip_fw_types.h"
|
||||
|
||||
/* For va_list */
|
||||
#include <stdarg.h>
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Function prototypes
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Initialisation Functions
|
||||
//
|
||||
|
||||
#if RTOS == NONE
|
||||
|
||||
MEDIAIP_FW_STATUS pal_initialise ( psPALConfig pconfig );
|
||||
|
||||
#else
|
||||
|
||||
void pal_early_initialise ( void );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_initialise ( void );
|
||||
|
||||
#endif
|
||||
|
||||
//////////////////////////////////////////////////
|
||||
// Assert function
|
||||
//
|
||||
void pal_assert_impl(u_int32 uAssertPC, u_int32 uAssertInfo);
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Critical section functions
|
||||
//
|
||||
|
||||
MEDIAIP_FW_STATUS pal_critical_section_begin ( PAL_CRIT_STATE *pState );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_critical_section_end ( PAL_CRIT_STATE PreviousState );
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Interrupt Functions
|
||||
//
|
||||
|
||||
MEDIAIP_FW_STATUS pal_int_register ( u_int32 dwIntID,
|
||||
PAL_PFNISR pfnHandler,
|
||||
BOOL bFIQ );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_int_enable ( u_int32 dwIntID );
|
||||
|
||||
void pal_int_set ( u_int32 dwIntID );
|
||||
|
||||
#if ( TARGET_PLATFORM == GENTB_PLATFORM ) || ( TARGET_PLATFORM == GEN_TB_ENC ) || ( TARGET_PLATFORM == WIN_LIB )
|
||||
|
||||
void pal_int_clear ( u_int32 dwIntID,
|
||||
BOOL bDirect );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_int_get_irq_line ( u_int32 uFWIrq,
|
||||
u_int32 *puIrqLine );
|
||||
|
||||
#else
|
||||
|
||||
void pal_int_clear ( u_int32 dwIntID );
|
||||
|
||||
#endif
|
||||
|
||||
void pal_int_clear_host ( u_int32 dwIntID );
|
||||
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Processor Cache Control Functions
|
||||
//
|
||||
|
||||
MEDIAIP_FW_STATUS pal_clean_d_cache ( void );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_disable_d_cache ( void );
|
||||
|
||||
void pal_wait_for_interrupt ( void );
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Malone Cache Control Functions
|
||||
//
|
||||
void pal_set_malone_cache ( u_int32 uMalID );
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// C Runtime Wrappers
|
||||
//
|
||||
|
||||
MEDIAIP_FW_STATUS pal_memcpy ( void *pDest,
|
||||
const void *pSrc,
|
||||
u_int32 uSize );
|
||||
|
||||
void pal_memset ( void *pDest, int32 nChar, u_int32 uCount );
|
||||
|
||||
BOOL pal_memcompare ( void *pArea1, void *pArea2, u_int32 uSizeInWords );
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Hardware Timer Service APIs
|
||||
//
|
||||
|
||||
MEDIAIP_FW_STATUS pal_timer_create ( PAL_PFNTIMER pfnCallback,
|
||||
void * pUserData,
|
||||
PAL_TIMER_ID * pTimer );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_timer_destroy( PAL_TIMER_ID Timer );
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Perf Counter APIs
|
||||
//
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_create ( const char * pszName,
|
||||
PAL_PERF_ID * pPCId );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_destroy ( PAL_PERF_ID PCId );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_start ( PAL_PERF_ID PCId );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_stop ( PAL_PERF_ID PCId );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_pause_control ( PAL_PERF_ID PCId , bool bStartPause);
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_read ( PAL_PERF_ID PerfId,
|
||||
u_int32 * puCountVal );
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Trace / Error / Message log functions
|
||||
//
|
||||
|
||||
/* Error logging */
|
||||
#if !(DEBUG_CAPS == FULL_DEBUG ) && (ENABLE_TRACE_IN_RELEASE == NO)
|
||||
|
||||
/* Non-debug case */
|
||||
MEDIAIP_FW_STATUS pal_error_log ( u_int32 uError );
|
||||
|
||||
#else
|
||||
|
||||
/* Debug case - wrap in macros so that we can add file and line number automatically */
|
||||
#ifdef _MSC_VER
|
||||
int pal_debug_error_log (
|
||||
#else
|
||||
MEDIAIP_FW_STATUS pal_debug_error_log (
|
||||
#endif
|
||||
u_int32 uError,
|
||||
char *pszFile,
|
||||
int32 nLineNum );
|
||||
#ifndef _MSC_VER
|
||||
#define pal_error_log(x) pal_debug_error_log((x), __FILE__, __LINE__)
|
||||
#endif // _MSC_VER
|
||||
#endif
|
||||
|
||||
/* Size of trace print buffer */
|
||||
#define FW_PRT_BUFF_SIZE 512
|
||||
|
||||
#ifdef DISABLE_TRACE
|
||||
/* Declare pal_trace as an empty statement and cast to void to avoid a "no-effect" warning. */
|
||||
/* This soaks up the trailing semi-colon and avoids leaving them dangling. */
|
||||
#define pal_trace(...) (void)(0)
|
||||
#else
|
||||
#if ( TARGET_APP == VPU_TEST_APP )
|
||||
#ifdef NXP_MX_REAL_TARGET
|
||||
#define pal_trace(flags, fmt, arg...) dprintf(LVL_FUNC, fmt, ## arg)
|
||||
#else
|
||||
void pal_trace ( u_int32 uFlags, const char *psz_format, ...);
|
||||
#endif
|
||||
#else
|
||||
void pal_trace ( u_int32 uFlags, const char *psz_format, ...);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int pal_vsnprintf ( char *str, int size, const char *format, va_list args );
|
||||
|
||||
int pal_sprintf ( char *str, int size, const char *psz_format, ...);
|
||||
|
||||
#ifdef PAL_DEBUG_LOG
|
||||
void pal_debug_log ( u_int32 uCode );
|
||||
#else
|
||||
#define pal_debug_log(...) (void)(0)
|
||||
#endif
|
||||
|
||||
MEDIAIP_FW_STATUS pal_trace_set_level ( u_int32 uLevel,
|
||||
BOOL bTimestamp,
|
||||
MEDIAIP_TRACE_FLAGS * pFlags );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_trace_set_module_flag ( u_int32 uModuleID,
|
||||
BOOL bEnable,
|
||||
MEDIAIP_TRACE_FLAGS * pFlags );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_trace_is_module_enabled ( u_int32 uModuleID,
|
||||
BOOL * pbEnabled );
|
||||
|
||||
void pal_checkpoint_str(char *pMsg );
|
||||
void pal_checkpoint_hex(unsigned uData);
|
||||
#define CHECKPOINT_STR pal_checkpoint_str
|
||||
#define CHECKPOINT_HEX pal_checkpoint_hex
|
||||
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Clock functions - often very platform specific
|
||||
//
|
||||
|
||||
#ifdef PAL_CLOCK_API
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_reg_init ( void );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_common ( bool bEnable );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_avc ( bool bEnable );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_vc1 ( bool bEnable );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_mpg ( bool bEnable );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_avs ( bool bEnable );
|
||||
|
||||
#endif /* PAL_CLOCK_API */
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Miscellaneous functions
|
||||
//
|
||||
|
||||
void pal_fatal_exit_internal ( u_int32 uCosmicConstant,
|
||||
char * pszFilename,
|
||||
int iLineNum );
|
||||
|
||||
//#define pal_fatal_exit(x) pal_fatal_exit_internal((x), __FILE__, __LINE__)
|
||||
#ifdef VPU_KERNEL_BUILD
|
||||
#define pal_fatal_exit(x) while (1) {printk("pal_fatal_exit in %s file %s line %d\n", __FUNCTION__, __FILE__, __LINE__);}
|
||||
#else
|
||||
#define pal_fatal_exit(x) while (1) {printf("pal_fatal_exit in %s file %s line %d\n", __FUNCTION__, __FILE__, __LINE__);}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
u_int32 pal_find_highest_bit ( u_int32 uValue );
|
||||
|
||||
extern u_int32 _return_pc ( void );
|
||||
|
||||
#define pal_return_pc _return_pc
|
||||
|
||||
u_int32 pal_get_fw_base ( void );
|
||||
|
||||
u_int32 pal_get_target_version ( void );
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Memory management abstraction functions
|
||||
//
|
||||
#if ( TARGET_APP == VPU_TEST_APP )
|
||||
/* sPALMemDesc Added by NXP for their PAL implementation */
|
||||
typedef struct {
|
||||
u_int32 size;
|
||||
u_int32 phy_addr;
|
||||
uint_addr virt_addr;
|
||||
#ifdef USE_ION
|
||||
int32 ion_buf_fd;
|
||||
#endif
|
||||
} sPALMemDesc, *psPALMemDesc;
|
||||
|
||||
MEDIAIP_FW_STATUS pal_get_phy_buf(psPALMemDesc pbuf);
|
||||
MEDIAIP_FW_STATUS pal_free_phy_buf(psPALMemDesc pbuf);
|
||||
#endif
|
||||
|
||||
u_int32 pal_va2pa ( u_int32 * pAddr );
|
||||
|
||||
u_int32 * pal_return_uncached_addr ( u_int32 * puAddress );
|
||||
|
||||
u_int32 * pal_return_cacheable_addr ( u_int32 * puAddress );
|
||||
|
||||
u_int32 * pal_return_mmu_bypass_addr ( u_int32 * puAddress );
|
||||
|
||||
u_int32 pal_read_uncached ( u_int32 * puAddress );
|
||||
|
||||
#if RTOS != NONE
|
||||
/* Need to add in the prototypes for the PAL ftns which invoke an OS */
|
||||
/* Abstraction layer call */
|
||||
|
||||
#include "pal_os_al.h"
|
||||
|
||||
#endif
|
||||
|
||||
///////////////////////////////////////////////////
|
||||
// Miscellaneous macros
|
||||
//
|
||||
|
||||
#ifdef PERF_MEASURE_ENABLE_ENC
|
||||
u_int32 GetCountVal();
|
||||
u_int32 SetCountVal(u_int32 CountVal);
|
||||
#endif
|
||||
|
||||
#if ( TARGET_APP == VPU_TEST_APP )
|
||||
#define INT_ID_MALONE_LOW 0
|
||||
#define INT_ID_MALONE_HI 1
|
||||
#define INT_ID_MAX 2
|
||||
extern PAL_PFNISR int_handlers[INT_ID_MAX];
|
||||
#endif
|
||||
|
||||
#endif /* _PAL_H_ */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
Filename : status_codes.h
|
||||
Description : Public header file for FW & SW status codes
|
||||
including those used by relevant abstraction layers
|
||||
Author : Kyle McAdoo
|
||||
|
||||
*****************************************************/
|
||||
|
||||
#ifndef _STATUS_CODES_H_
|
||||
#define _STATUS_CODES_H_
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/* 0 0x00 */ MEDIAIP_FW_STATUS_OK = 0,
|
||||
/* 1 0x01 */ MEDIAIP_FW_STATUS_ALREADY_INIT,
|
||||
/* 2 0x02 */ MEDIAIP_FW_STATUS_NOT_INIT,
|
||||
/* 3 0x03 */ MEDIAIP_FW_STATUS_INTERNAL_ERROR,
|
||||
/* 4 0x04 */ MEDIAIP_FW_STATUS_BAD_HANDLE,
|
||||
/* 5 0x05 */ MEDIAIP_FW_STATUS_BAD_PARAMETER,
|
||||
/* 6 0x06 */ MEDIAIP_FW_STATUS_BAD_LENGTH,
|
||||
/* 7 0x07 */ MEDIAIP_FW_STATUS_BAD_UNIT,
|
||||
/* 8 0x08 */ MEDIAIP_FW_STATUS_RESOURCE_ERROR,
|
||||
/* 9 0x09 */ MEDIAIP_FW_STATUS_CLOSED_HANDLE,
|
||||
/* 10 0x0A */ MEDIAIP_FW_STATUS_TIMEOUT,
|
||||
/* 11 0x0B */ MEDIAIP_FW_STATUS_NOT_ATTACHED,
|
||||
/* 12 0x0C */ MEDIAIP_FW_STATUS_NOT_SUPPORTED,
|
||||
/* 13 0x0D */ MEDIAIP_FW_STATUS_REOPENED_HANDLE,
|
||||
/* 14 0x0E */ MEDIAIP_FW_STATUS_INVALID,
|
||||
/* 15 0x0F */ MEDIAIP_FW_STATUS_DESTROYED,
|
||||
/* 16 0x10 */ MEDIAIP_FW_STATUS_DISCONNECTED,
|
||||
/* 17 0x11 */ MEDIAIP_FW_STATUS_BUSY,
|
||||
/* 18 0x12 */ MEDIAIP_FW_STATUS_IN_USE,
|
||||
/* 19 0x13 */ MEDIAIP_FW_STATUS_CANCELLED,
|
||||
/* 20 0x14 */ MEDIAIP_FW_STATUS_UNDEFINED,
|
||||
/* 21 0x15 */ MEDIAIP_FW_STATUS_UNKNOWN,
|
||||
/* 22 0x16 */ MEDIAIP_FW_STATUS_NOT_FOUND,
|
||||
/* 23 0x17 */ MEDIAIP_FW_STATUS_NOT_AVAILABLE,
|
||||
/* 24 0x18 */ MEDIAIP_FW_STATUS_NOT_COMPATIBLE,
|
||||
/* 25 0x19 */ MEDIAIP_FW_STATUS_NOT_IMPLEMENTED,
|
||||
/* 26 0x1A */ MEDIAIP_FW_STATUS_EMPTY,
|
||||
/* 27 0x1B */ MEDIAIP_FW_STATUS_FULL,
|
||||
/* 28 0x1C */ MEDIAIP_FW_STATUS_FAILURE,
|
||||
/* 29 0x1D */ MEDIAIP_FW_STATUS_ALREADY_ATTACHED,
|
||||
/* 30 0x1E */ MEDIAIP_FW_STATUS_ALREADY_DONE,
|
||||
/* 31 0x1F */ MEDIAIP_FW_STATUS_ASLEEP,
|
||||
/* 32 0x20 */ MEDIAIP_FW_STATUS_BAD_ATTACHMENT,
|
||||
/* 33 0x21 */ MEDIAIP_FW_STATUS_BAD_COMMAND,
|
||||
/* 34 0x22 */ MEDIAIP_FW_STATUS_INT_HANDLED,
|
||||
/* 35 0x23 */ MEDIAIP_FW_STATUS_INT_NOT_HANDLED,
|
||||
/* 36 0x24 */ MEDIAIP_FW_STATUS_NOT_SET,
|
||||
/* 37 0x25 */ MEDIAIP_FW_STATUS_NOT_HOOKED,
|
||||
/* 38 0x26 */ MEDIAIP_FW_STATUS_COMPLETE,
|
||||
/* 39 0x27 */ MEDIAIP_FW_STATUS_INVALID_NODE,
|
||||
/* 40 0x28 */ MEDIAIP_FW_STATUS_DUPLICATE_NODE,
|
||||
/* 41 0x29 */ MEDIAIP_FW_STATUS_HARDWARE_NOT_FOUND,
|
||||
/* 42 0x2A */ MEDIAIP_FW_STATUS_ILLEGAL_OPERATION,
|
||||
/* 43 0x2B */ MEDIAIP_FW_STATUS_INCOMPATIBLE_FORMATS,
|
||||
/* 44 0x2C */ MEDIAIP_FW_STATUS_INVALID_DEVICE,
|
||||
/* 45 0x2D */ MEDIAIP_FW_STATUS_INVALID_EDGE,
|
||||
/* 46 0x2E */ MEDIAIP_FW_STATUS_INVALID_NUMBER,
|
||||
/* 47 0x2F */ MEDIAIP_FW_STATUS_INVALID_STATE,
|
||||
/* 48 0x30 */ MEDIAIP_FW_STATUS_INVALID_TYPE,
|
||||
/* 49 0x31 */ MEDIAIP_FW_STATUS_STOPPED,
|
||||
/* 50 0x32 */ MEDIAIP_FW_STATUS_SUSPENDED,
|
||||
/* 51 0x33 */ MEDIAIP_FW_STATUS_TERMINATED,
|
||||
/* 52 0x34 */ MEDIAIP_FW_STATUS_FRAMESTORE_NOT_HANDLED,
|
||||
/* Last Entry */ MEDIAIP_FW_STATUS_CODE_LAST = MEDIAIP_FW_STATUS_FRAMESTORE_NOT_HANDLED
|
||||
} MEDIAIP_FW_STATUS;
|
||||
|
||||
#if RTOS != NONE
|
||||
|
||||
#if OSAL == CNXT_KAL
|
||||
#include "cnxt_kal_status_codes.h"
|
||||
typedef MEDIAIP_OSAL_STATUS CNXT_IRQ_RETCODE;
|
||||
typedef MEDIAIP_FW_STATUS MEDIAIP_IRQ_RETCODE;
|
||||
#endif
|
||||
|
||||
#if OSAL == NXP_OSAL
|
||||
#include "nxp_osal_status_codes.h"
|
||||
typedef MEDIAIP_OSAL_STATUS MEDIAIP_IRQ_RETCODE;
|
||||
#endif
|
||||
|
||||
#else
|
||||
typedef MEDIAIP_FW_STATUS MEDIAIP_IRQ_RETCODE;
|
||||
#endif
|
||||
|
||||
#endif /* _STATUS_CODES_H_ */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,261 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
Filename : trace_types.h
|
||||
Description : Public header file containing type definitions and labels
|
||||
related to debug trace functions
|
||||
Author : Dave Wilson
|
||||
Modified for Transcode FW by K McAdoo (from version 1.41)
|
||||
This is no longer only for RTOS builds
|
||||
************************************************/
|
||||
|
||||
#ifndef _TRACE_TYPES_H_
|
||||
#define _TRACE_TYPES_H_
|
||||
|
||||
#include "basetype.h"
|
||||
|
||||
/* Flag indicating a fatal error - top bit of error_num */
|
||||
#define MEDIAIP_ERROR_FATAL 0x80000000
|
||||
#define MEDIAIP_ERROR_WARNING 0x00000000
|
||||
|
||||
/* Flags for trace levels */
|
||||
#define MEDIAIP_TRACE_MASK_MODULE 0x0FFFFFFF
|
||||
#define MEDIAIP_TRACE_MASK_LEVEL 0x70000000
|
||||
#define MEDIAIP_TRACE_MASK_TIMESTAMP 0x80000000
|
||||
|
||||
#define MEDIAIP_TRACE_SHIFT_LEVEL 28
|
||||
#define MEDIAIP_TRACE_SHIFT_TIMESTAMP 31
|
||||
|
||||
#define MEDIAIP_TRACE_LEVEL_NEVER 0x00000000
|
||||
#define MEDIAIP_TRACE_LEVEL_1 0x10000000
|
||||
#define MEDIAIP_TRACE_LEVEL_2 0x20000000
|
||||
#define MEDIAIP_TRACE_LEVEL_3 0x30000000
|
||||
#define MEDIAIP_TRACE_LEVEL_4 0x40000000
|
||||
#define MEDIAIP_TRACE_LEVEL_5 0x50000000
|
||||
#define MEDIAIP_TRACE_LEVEL_6 0x60000000
|
||||
#define MEDIAIP_TRACE_LEVEL_ALWAYS 0x70000000
|
||||
|
||||
/* Disable the timestamp */
|
||||
#define MEDIAIP_TRACE_NO_TIMESTAMP 0x80000000
|
||||
|
||||
/* Module identifiers */
|
||||
#define MEDIAIP_TRACE_DECODER 0x00000001
|
||||
#define MEDIAIP_TRACE_DISPLAY 0x00000002
|
||||
#define MEDIAIP_TRACE_ENCODER 0x00000003
|
||||
#define MEDIAIP_TRACE_HANDLE 0x00000004
|
||||
#define MEDIAIP_TRACE_IMGPORT 0x00000005
|
||||
#define MEDIAIP_TRACE_PAL 0x00000006
|
||||
#define MEDIAIP_TRACE_KAL 0x00000006
|
||||
#define MEDIAIP_TRACE_MEMMOVE 0x00000007
|
||||
#define MEDIAIP_TRACE_QUEUE 0x00000008
|
||||
#define MEDIAIP_TRACE_VAMUX 0x00000009
|
||||
|
||||
/* Control Layer identifiers */
|
||||
#define MEDIAIP_TRACE_VIDEO_LAYER 0x00000050
|
||||
#define MEDIAIP_TRACE_SYSTEM_LAYER 0x00000051
|
||||
#define MEDIAIP_TRACE_PROC_LAYER 0x00000052
|
||||
#define MEDIAIP_TRACE_API_LAYER 0x00000053
|
||||
|
||||
/* Additional IDs for application use */
|
||||
#define MEDIAIP_TRACE_APPLICATION 0x00000060
|
||||
#define MEDIAIP_TRACE_TEST 0x00000061
|
||||
|
||||
/* The upper supported value of a trace module identifier. Make sure that
|
||||
there are no trace IDs defined above this value since it is used to
|
||||
determine the amount of storage required for trace flags! */
|
||||
#define MEDIAIP_TRACE_MAX 0x0000009F
|
||||
|
||||
/* ID indicating that message should be displayed regardless of the
|
||||
modules which are currently enabled. */
|
||||
#define MEDIAIP_TRACE_ANY 0x00000000
|
||||
|
||||
/* Trace message color codes */
|
||||
|
||||
#define MEDIAIP_TRACE_FG_LIGHT_BLUE "\033[1;34m"
|
||||
#define MEDIAIP_TRACE_FG_LIGHT_GREEN "\033[1;32m"
|
||||
#define MEDIAIP_TRACE_FG_LIGHT_CYAN "\033[1;36m"
|
||||
#define MEDIAIP_TRACE_FG_LIGHT_RED "\033[1;31m"
|
||||
#define MEDIAIP_TRACE_FG_WHITE "\033[1;37m"
|
||||
#define MEDIAIP_TRACE_FG_NORMAL MEDIAIP_TRACE_FG_WHITE
|
||||
#define MEDIAIP_TRACE_BG_GRAY "\033[0;47m"
|
||||
#define MEDIAIP_TRACE_BG_BLACK "\033[0;40m"
|
||||
|
||||
/* The number of 32bit words needed to store our trace flags */
|
||||
#define MEDIAIP_TRACE_FLAGS_WORDS ((MEDIAIP_TRACE_MAX+31)/32)
|
||||
|
||||
/* Data structure used to store trace flags */
|
||||
typedef struct
|
||||
{
|
||||
|
||||
u_int32 Flags[MEDIAIP_TRACE_FLAGS_WORDS];
|
||||
|
||||
} MEDIAIP_TRACE_FLAGS;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Module / Application and System Trace level definitions
|
||||
|
||||
#define DECODER_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define DECODER_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_DECODER)
|
||||
#define DECODER_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_DECODER)
|
||||
#define DECODER_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_DECODER)
|
||||
#define DECODER_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_DECODER)
|
||||
#define DECODER_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_DECODER)
|
||||
#define DECODER_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_DECODER)
|
||||
#define DECODER_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_DECODER)
|
||||
|
||||
#define DISPLAY_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define DISPLAY_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_DISPLAY)
|
||||
#define DISPLAY_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_DISPLAY)
|
||||
#define DISPLAY_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_DISPLAY)
|
||||
#define DISPLAY_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_DISPLAY)
|
||||
#define DISPLAY_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_DISPLAY)
|
||||
#define DISPLAY_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_DISPLAY)
|
||||
#define DISPLAY_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_DISPLAY)
|
||||
|
||||
#define ENCODER_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define ENCODER_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ENCODER)
|
||||
#define ENCODER_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_ENCODER)
|
||||
#define ENCODER_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_ENCODER)
|
||||
#define ENCODER_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_ENCODER)
|
||||
#define ENCODER_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_ENCODER)
|
||||
#define ENCODER_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_ENCODER)
|
||||
#define ENCODER_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_ENCODER)
|
||||
|
||||
#define HANDLE_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define HANDLE_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_HANDLE)
|
||||
#define HANDLE_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_HANDLE)
|
||||
#define HANDLE_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_HANDLE)
|
||||
#define HANDLE_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_HANDLE)
|
||||
#define HANDLE_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_HANDLE)
|
||||
#define HANDLE_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_HANDLE)
|
||||
#define HANDLE_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_HANDLE)
|
||||
|
||||
#define IMGPORT_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define IMGPORT_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_IMGPORT)
|
||||
#define IMGPORT_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_IMGPORT)
|
||||
#define IMGPORT_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_IMGPORT)
|
||||
#define IMGPORT_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_IMGPORT)
|
||||
#define IMGPORT_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_IMGPORT)
|
||||
#define IMGPORT_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_IMGPORT)
|
||||
#define IMGPORT_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_IMGPORT)
|
||||
|
||||
#define KAL_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define KAL_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_KAL)
|
||||
#define KAL_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_KAL)
|
||||
#define KAL_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_KAL)
|
||||
#define KAL_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_KAL)
|
||||
#define KAL_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_KAL)
|
||||
#define KAL_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_KAL)
|
||||
#define KAL_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_KAL)
|
||||
|
||||
#define PAL_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define PAL_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_PAL)
|
||||
#define PAL_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_PAL)
|
||||
#define PAL_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_PAL)
|
||||
#define PAL_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_PAL)
|
||||
#define PAL_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_PAL)
|
||||
#define PAL_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_PAL)
|
||||
#define PAL_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_PAL)
|
||||
|
||||
#define MEMMOVE_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define MEMMOVE_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_MEMMOVE)
|
||||
#define MEMMOVE_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_MEMMOVE)
|
||||
#define MEMMOVE_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_MEMMOVE)
|
||||
#define MEMMOVE_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_MEMMOVE)
|
||||
#define MEMMOVE_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_MEMMOVE)
|
||||
#define MEMMOVE_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_MEMMOVE)
|
||||
#define MEMMOVE_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_MEMMOVE)
|
||||
|
||||
#define QUEUE_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define QUEUE_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_QUEUE)
|
||||
#define QUEUE_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_QUEUE)
|
||||
#define QUEUE_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_QUEUE)
|
||||
#define QUEUE_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_QUEUE)
|
||||
#define QUEUE_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_QUEUE)
|
||||
#define QUEUE_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_QUEUE)
|
||||
#define QUEUE_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_QUEUE)
|
||||
|
||||
#define VAMUX_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define VAMUX_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_VAMUX)
|
||||
#define VAMUX_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_VAMUX)
|
||||
#define VAMUX_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_VAMUX)
|
||||
#define VAMUX_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_VAMUX)
|
||||
#define VAMUX_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_VAMUX)
|
||||
#define VAMUX_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_VAMUX)
|
||||
#define VAMUX_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_VAMUX)
|
||||
|
||||
#define VIDEO_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define VIDEO_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_VIDEO_LAYER)
|
||||
#define VIDEO_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_VIDEO_LAYER)
|
||||
#define VIDEO_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_VIDEO_LAYER)
|
||||
#define VIDEO_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_VIDEO_LAYER)
|
||||
#define VIDEO_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_VIDEO_LAYER)
|
||||
#define VIDEO_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_VIDEO_LAYER)
|
||||
#define VIDEO_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_VIDEO_LAYER)
|
||||
|
||||
#define SYSTEM_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define SYSTEM_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_SYSTEM_LAYER)
|
||||
#define SYSTEM_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_SYSTEM_LAYER)
|
||||
#define SYSTEM_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_SYSTEM_LAYER)
|
||||
#define SYSTEM_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_SYSTEM_LAYER)
|
||||
#define SYSTEM_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_SYSTEM_LAYER)
|
||||
#define SYSTEM_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_SYSTEM_LAYER)
|
||||
#define SYSTEM_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_SYSTEM_LAYER)
|
||||
|
||||
#define PROC_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define PROC_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_PROC_LAYER)
|
||||
#define PROC_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_PROC_LAYER)
|
||||
#define PROC_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_PROC_LAYER)
|
||||
#define PROC_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_PROC_LAYER)
|
||||
#define PROC_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_PROC_LAYER)
|
||||
#define PROC_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_PROC_LAYER)
|
||||
#define PROC_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_PROC_LAYER)
|
||||
|
||||
#define API_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define API_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_API_LAYER)
|
||||
#define API_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_API_LAYER)
|
||||
#define API_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_API_LAYER)
|
||||
#define API_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_API_LAYER)
|
||||
#define API_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_API_LAYER)
|
||||
#define API_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_API_LAYER)
|
||||
#define API_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_API_LAYER)
|
||||
|
||||
#define APP_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define APP_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_APPLICATION)
|
||||
#define APP_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_APPLICATION)
|
||||
#define APP_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_APPLICATION)
|
||||
#define APP_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_APPLICATION)
|
||||
#define APP_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_APPLICATION)
|
||||
#define APP_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_APPLICATION)
|
||||
#define APP_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_APPLICATION)
|
||||
|
||||
#define TEST_TL_CATASTROPHE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_ANY)
|
||||
#define TEST_TL_SEVERE (MEDIAIP_TRACE_LEVEL_ALWAYS | MEDIAIP_TRACE_TEST)
|
||||
#define TEST_TL_ERROR (MEDIAIP_TRACE_LEVEL_6 | MEDIAIP_TRACE_TEST)
|
||||
#define TEST_TL_WARNING (MEDIAIP_TRACE_LEVEL_5 | MEDIAIP_TRACE_TEST)
|
||||
#define TEST_TL_FUNC (MEDIAIP_TRACE_LEVEL_4 | MEDIAIP_TRACE_TEST)
|
||||
#define TEST_TL_INFO (MEDIAIP_TRACE_LEVEL_3 | MEDIAIP_TRACE_TEST)
|
||||
#define TEST_TL_VERBOSE (MEDIAIP_TRACE_LEVEL_2 | MEDIAIP_TRACE_TEST)
|
||||
#define TEST_TL_DEBUG (MEDIAIP_TRACE_LEVEL_1 | MEDIAIP_TRACE_TEST)
|
||||
|
||||
#if RTOS != NONE
|
||||
#if OSAL == CNXT_KAL
|
||||
|
||||
typedef MEDIAIP_TRACE_FLAGS CNXT_TRACE_FLAGS;
|
||||
|
||||
#endif /* OSAL == CNXT_KAL */
|
||||
#endif /* RTOS != NOOS */
|
||||
|
||||
#endif /* _TRACE_TYPES_H_ */
|
||||
|
||||
|
||||
/* End of file */
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/***********************************************
|
||||
* Copyright (c) 2015 Amphion Semiconductor Ltd *
|
||||
***********************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
*
|
||||
* Filename: pal_linux_map.h
|
||||
* Description: Maps the abstraction layer type from the
|
||||
* PAL to Linux defines, though a variation of CNXT KAL
|
||||
* for implementing NXP PAL implementaiton layer
|
||||
* Author: Media IP FW team (Belfast)
|
||||
*
|
||||
******************************************************************************
|
||||
* $Id:
|
||||
******************************************************************************/
|
||||
|
||||
/* Note : At the moment I have done no real comparison and merge of the
|
||||
different abstarction layers supported in the PAL layer so this
|
||||
file is simply a direct map - currently its only ftn is to
|
||||
remove compiler warnings and to get the code structure correct for
|
||||
the future
|
||||
*/
|
||||
|
||||
#ifndef _PAL_LINUX_MAP_H_
|
||||
#define _PAL_LINUX_MAP_H_
|
||||
|
||||
#include "status_codes.h"
|
||||
|
||||
/*******************/
|
||||
/* Resource Limits */
|
||||
/*******************/
|
||||
|
||||
#if 0
|
||||
/* Maximum length of an OS object name string */
|
||||
#define PAL_MAX_OBJ_NAME_LENGTH CNXT_KAL_MAX_OBJ_NAME_LENGTH
|
||||
#endif
|
||||
|
||||
#define PAL_NO_WAIT 0
|
||||
#define PAL_WAIT_FOREVER ((u_int32)-1)
|
||||
|
||||
#if 0
|
||||
/* Macro to assign task priority based on RTOS */
|
||||
#define PAL_THREAD_PRIO(Prio, UCOS_Prio) CNXT_KAL_THREAD_PRIO(Prio, UCOS_Prio)
|
||||
|
||||
/* Task Priority Limits. */
|
||||
#define PAL_DEFAULT_PRIORITY CNXT_KAL_DEFAULT_PRIORITY
|
||||
#define PAL_MAX_THREAD_PRIORITY CNXT_KAL_MAX_THREAD_PRIORITY
|
||||
#define PAL_MIN_THREAD_PRIORITY CNXT_KAL_MIN_THREAD_PRIORITY
|
||||
#endif
|
||||
|
||||
/* Object identifiers, KAL originated */
|
||||
typedef u_int32 CNXT_QUEUE_ID;
|
||||
typedef u_int32 CNXT_THREAD_ID;
|
||||
typedef u_int32 CNXT_SEM_ID;
|
||||
typedef u_int32 CNXT_MUTEX_ID;
|
||||
typedef u_int32 CNXT_POOL_ID;
|
||||
typedef u_int16 CNXT_EVENTS;
|
||||
typedef u_int32 CNXT_TICK_ID;
|
||||
typedef u_int32 CNXT_TIMER_ID;
|
||||
typedef bool CNXT_CRIT_STATE;
|
||||
|
||||
#define PAL_QUEUE_ID CNXT_QUEUE_ID
|
||||
#define PAL_THREAD_ID CNXT_THREAD_ID
|
||||
#define PAL_SEM_ID CNXT_SEM_ID
|
||||
#define PAL_POOL_ID CNXT_POOL_ID
|
||||
#define PAL_EVENTS CNXT_EVENTS
|
||||
#define PAL_TICK_ID CNXT_TICK_ID
|
||||
#define PAL_TIMER_ID CNXT_TIMER_ID
|
||||
#define PAL_CRIT_STATE CNXT_CRIT_STATE
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PAL_CB_LOW_PRIORITY,
|
||||
PAL_CB_LOW_PRIORITY_NO_BLOCK,
|
||||
PAL_CB_HIGH_PRIORITY,
|
||||
PAL_CB_HIGH_PRIORITY_NO_BLOCK,
|
||||
PAL_CB_PRIORITY_LAST = PAL_CB_HIGH_PRIORITY_NO_BLOCK
|
||||
} PAL_CB_PRIORITY;
|
||||
|
||||
#define PAL_PFNTHREAD PFNTHREAD
|
||||
#define PAL_PFNISR PFNISR
|
||||
#define PAL_PFNTHREADCALLBACK PFNTHREADCALLBACK
|
||||
typedef void (*PFNTHREAD)(int, void **);
|
||||
typedef MEDIAIP_FW_STATUS (*PFNISR)(u_int32);
|
||||
typedef void (*PFNTHREADCALLBACK)(u_int32, u_int32, void *);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*****************************************************************/
|
||||
/** PAL functions exporting OS abstraction layer functionality **/
|
||||
/*****************************************************************/
|
||||
|
||||
MEDIAIP_FW_STATUS pal_thread_create ( PAL_PFNTHREAD pfnEntryPoint,
|
||||
int nArgC,
|
||||
void **ppArgV,
|
||||
u_int32 uStackSize,
|
||||
u_int8 uPrio,
|
||||
const char *pszName,
|
||||
PAL_THREAD_ID *pId );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_thread_terminate ( PAL_THREAD_ID *pId );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_make_async_thread_callback (
|
||||
PAL_PFNTHREADCALLBACK pfnCallback,
|
||||
PAL_CB_PRIORITY Priority,
|
||||
u_int32 uParam1,
|
||||
u_int32 uParam2,
|
||||
void *pData );
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Semaphore functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_FW_STATUS pal_sem_create ( u_int32 uInitialValue,
|
||||
const char *pszName,
|
||||
PAL_SEM_ID *pSem);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Queue functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_create ( unsigned int nMaxElements,
|
||||
const char *pszName,
|
||||
PAL_QUEUE_ID *pQuId );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_destroy ( PAL_QUEUE_ID QuId );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_send ( PAL_QUEUE_ID QuId,
|
||||
void *pMessage );
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_receive ( PAL_QUEUE_ID QuId,
|
||||
u_int32 uTimeoutMs,
|
||||
void *pMessage );
|
||||
|
||||
|
||||
#endif /* _PAL_CNXT_KAL_MAP_H_ */
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/***************************************************
|
||||
Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
All rights reserved.
|
||||
***************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
|
||||
Filename: pal_types.h
|
||||
Description: Public header file for PAL type definitions
|
||||
Common between all platforms
|
||||
Author: Media IP FW team (Belfast)
|
||||
|
||||
****************************************************/
|
||||
|
||||
#ifndef _PAL_TYPES_H_
|
||||
#define _PAL_TYPES_H_
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Header Files
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "basetype.h"
|
||||
#include "status_codes.h"
|
||||
#include "trace_types.h"
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Macros
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Define the magic cookie
|
||||
#define PAL_CONFIG_MAGIC 0x434C4150 // "PALC", little endian
|
||||
|
||||
// Values for pal_trace_destination
|
||||
#define PAL_TRACE_TO_DEVNULL 0
|
||||
#define PAL_TRACE_TO_UART 1
|
||||
#define PAL_TRACE_TO_MESSAGE 2
|
||||
#define PAL_TRACE_TO_CIRCULARBUF 3
|
||||
|
||||
#if ( TARGET_PLATFORM == GENTB_PLATFORM ) || ( TARGET_PLATFORM == WIN_LIB ) || ( TARGET_PLATFORM == GEN_TB_ENC )
|
||||
|
||||
#define PAL_CONFIG_MAX_IRQS 0x12
|
||||
#define PAL_CONFIG_MAX_MALONES 0x2
|
||||
#define PAL_CONFIG_MAX_WINDSORS 0x1
|
||||
#define PAL_CONFIG_MAX_TIMER_IRQS 0x4
|
||||
#define PAL_CONFIG_MAX_TIMER_SLOTS 0x4
|
||||
|
||||
/* Define the entry locations in the irq vector */
|
||||
#define PAL_IRQ_MALONE0_LOW 0x0
|
||||
#define PAL_IRQ_MALONE0_HI 0x1
|
||||
#define PAL_IRQ_MALONE1_LOW 0x2
|
||||
#define PAL_IRQ_MALONE1_HI 0x3
|
||||
#define PAL_IRQ_WINDSOR_LOW 0x4
|
||||
#define PAL_IRQ_WINDSOR_HI 0x5
|
||||
#define PAL_IRQ_HOST_CMD_LO 0x6
|
||||
#define PAL_IRQ_HOST_CMD_HI 0x7
|
||||
#define PAL_IRQ_HOST_MSG 0x9
|
||||
#define PAL_IRQ_DPV 0xA
|
||||
#define PAL_IRQ_TIMER_0 0xE
|
||||
#define PAL_IRQ_TIMER_1 0xF
|
||||
#define PAL_IRQ_TIMER_2 0x10
|
||||
#define PAL_IRQ_TIMER_3 0x11
|
||||
|
||||
#else
|
||||
|
||||
#define PAL_CONFIG_MAX_INITS 4 // Number of init slots
|
||||
#define PAL_CONFIG_MAX_IRQS 2 // Number of incoming irq lines supported
|
||||
|
||||
#endif /* TARGET_PLATFORM == TB_PLATFORM */
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Structure definitions
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#if OSAL == NO_AL
|
||||
/* Function pointer types */
|
||||
typedef u_int32 PAL_TIMER_ID;
|
||||
typedef u_int32 PAL_CRIT_STATE;
|
||||
|
||||
typedef MEDIAIP_IRQ_RETCODE (*PAL_PFNISR)(u_int32);
|
||||
typedef void (*PAL_PFNTIMER)(PAL_TIMER_ID, void *);
|
||||
|
||||
#endif
|
||||
|
||||
typedef u_int32 PAL_PERF_ID;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// PAL Configuration structure
|
||||
|
||||
#if ( TARGET_PLATFORM == GENTB_PLATFORM ) || ( TARGET_PLATFORM == WIN_LIB ) || ( TARGET_PLATFORM == GEN_TB_ENC )
|
||||
|
||||
typedef struct _PALConfig
|
||||
{
|
||||
u_int32 uPalConfigMagicCookie;
|
||||
|
||||
u_int32 uGICBaseAddr;
|
||||
u_int32 uIrqLines[PAL_CONFIG_MAX_IRQS];
|
||||
u_int32 uIrqTarget[PAL_CONFIG_MAX_IRQS];
|
||||
|
||||
u_int32 uUartBaseAddr;
|
||||
|
||||
u_int32 uSysClkFreq;
|
||||
u_int32 uNumTimers;
|
||||
u_int32 uTimerBaseAddr;
|
||||
u_int32 uTimerSlots[PAL_CONFIG_MAX_TIMER_SLOTS];
|
||||
|
||||
/* Do we need this in the PAL config? Only for checking mmu setup */
|
||||
/* perhaps - otherwise its more naturtal home is in the DECLIB_CFG */
|
||||
/* structure */
|
||||
u_int32 uNumMalones;
|
||||
u_int32 uMaloneBaseAddr[PAL_CONFIG_MAX_MALONES];
|
||||
u_int32 uHifOffset[PAL_CONFIG_MAX_MALONES];
|
||||
|
||||
u_int32 uNumWindsors;
|
||||
u_int32 uWindsorBaseAddr[PAL_CONFIG_MAX_WINDSORS];
|
||||
|
||||
u_int32 uDPVBaseAddr;
|
||||
u_int32 uPixIfAddr;
|
||||
|
||||
u_int32 pal_trace_level;
|
||||
// u_int32 pal_trace_destination;
|
||||
// u_int32 pal_trace_CBDescAddr[3]; // 3 separate circular buffers for PAL_TRACE_TO_CIRCULARBUF
|
||||
// 0: normal 1: irq 2: fiq
|
||||
u_int32 uHeapBase;
|
||||
u_int32 uHeapSize;
|
||||
|
||||
u_int32 uFSLCacheBaseAddr;
|
||||
|
||||
} sPALConfig, *psPALConfig;
|
||||
|
||||
#else
|
||||
|
||||
typedef struct _PALConfig
|
||||
{
|
||||
u_int32 pal_config_magic_cookie;
|
||||
u_int32 cmd_irq_line[PAL_CONFIG_MAX_IRQS];
|
||||
u_int32 cmd_irq_clear_addr[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 cmd_irq_clear_mask[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 cmd_irq_clear_val[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 msg_irq_init_addr[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 msg_irq_init_mask[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 msg_irq_init_val[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 msg_irq_raise_addr;
|
||||
u_int32 msg_irq_raise_mask;
|
||||
u_int32 msg_irq_raise_val;
|
||||
u_int32 uart_init_addr[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 uart_init_mask[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 uart_init_val[PAL_CONFIG_MAX_INITS];
|
||||
u_int32 uart_check_addr;
|
||||
u_int32 uart_check_mask;
|
||||
u_int32 uart_check_val;
|
||||
u_int32 uart_put_addr;
|
||||
u_int32 pal_trace_level;
|
||||
u_int32 pal_trace_destination;
|
||||
MEDIAIP_TRACE_FLAGS pal_trace_flags; // Currently 5 words
|
||||
u_int32 pal_trace_CBDescAddr[3]; // 3 separate circular buffers for PAL_TRACE_TO_CIRCULARBUF
|
||||
// 0: normal 1: irq 2: fiq
|
||||
} sPALConfig, *psPALConfig;
|
||||
|
||||
#endif /* TARGET_PLATFORM == TB_PLATFORM */
|
||||
|
||||
|
||||
#endif /* _PAL_TYPES_H_ */
|
||||
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -0,0 +1,772 @@
|
|||
/***************************************************
|
||||
* Copyright (c) 2015 Amphion Semiconductor Ltd
|
||||
* All rights reserved.
|
||||
****************************************************
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
****************************************************
|
||||
*
|
||||
* Filename : pal.c
|
||||
* Description : Code implementing Platform Abstraction Layer
|
||||
*
|
||||
* Author : Media IP FW team (Belfast)
|
||||
*
|
||||
****************************************************/
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//// Header Files
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <pthread.h>
|
||||
#include <sys/stat.h>
|
||||
#include <unistd.h>
|
||||
#include <fcntl.h>
|
||||
#include <sys/errno.h>
|
||||
#include "VPU_io.h"
|
||||
#else
|
||||
#undef ARM
|
||||
#undef SUCCESS
|
||||
#include <linux/io.h>
|
||||
#include <linux/kfifo.h>
|
||||
#include <linux/kthread.h>
|
||||
|
||||
#endif
|
||||
#include "pal.h"
|
||||
#include "VPU_regdef.h"
|
||||
#include "VPU_debug.h"
|
||||
#include "mvd.h"
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
//// External Function Prototypes
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// The function declared in pal.h is set to be empty
|
||||
// and need to be defined later
|
||||
|
||||
//volatile u_int32 guPlayerFlag[MEDIA_PLAYER_NUM_STREAMS];
|
||||
|
||||
#ifdef VPU_KERNEL_BUILD
|
||||
extern void __iomem *vpu_base;
|
||||
#define VPU_REG_WR(reg, val) writel(val, vpu_base + reg)
|
||||
#define VPU_REG_RD(reg) readl(vpu_base + reg)
|
||||
#else
|
||||
#define VPU_REG_WR(reg, val) VpuWriteReg(reg, val)
|
||||
#define VPU_REG_RD(reg) VpuReadReg(reg)
|
||||
#endif
|
||||
|
||||
PAL_PFNISR int_handlers[INT_ID_MAX];
|
||||
|
||||
#ifdef ENABLE_CRIT_SECTIONS
|
||||
static int ulCriticalNesting = 0;
|
||||
#endif
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////
|
||||
// Assert function, implementation to be defined but we want to use this to trap logical errors
|
||||
//
|
||||
bool gbAssertExit = FALSE;
|
||||
void pal_assert_impl(u_int32 uAssertPC, u_int32 uAssertInfo)
|
||||
{
|
||||
/* AssertInfo could be the offset address of the calling function or something else? */
|
||||
while(gbAssertExit==FALSE)
|
||||
{
|
||||
/* wait to allow debug */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
MEDIAIP_FW_STATUS pal_critical_section_begin ( PAL_CRIT_STATE *pState )
|
||||
{
|
||||
#ifdef ENABLE_CRIT_SECTIONS
|
||||
//ENTER_FUNC();
|
||||
if(ulCriticalNesting>0)
|
||||
dprintf(LVL_FUNC, "Nested %d\n", ulCriticalNesting);
|
||||
// FIXME: might need MFD_HIF_MSD_REG_HOST_INTERRUPT_ENABLE 0x1000
|
||||
*pState = VPU_REG_RD((DEC_MFD_XREG_SLV_BASE + MFD_HIF + MFD_HIF_MSD_REG_FAST_INTERRUPT_ENABLE));
|
||||
VPU_REG_WR((DEC_MFD_XREG_SLV_BASE + MFD_HIF + MFD_HIF_MSD_REG_FAST_INTERRUPT_ENABLE), *pState & ~0x20);
|
||||
//dprintf(LVL_FUNC, "save to State 0x%lx, expect 0x20 outside irq or 0 inside irq\n", *pState);
|
||||
ulCriticalNesting++;
|
||||
#endif
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_critical_section_end ( PAL_CRIT_STATE PreviousState )
|
||||
{
|
||||
#ifdef ENABLE_CRIT_SECTIONS
|
||||
ulCriticalNesting--;
|
||||
//ENTER_FUNC();
|
||||
//dprintf(LVL_FUNC, "Nest %d\n", ulCriticalNesting);
|
||||
//dprintf(LVL_FUNC, "restore from State 0x%lx, expect 0x20 outside irq or 0 inside irq\n", PreviousState);
|
||||
VPU_REG_WR((DEC_MFD_XREG_SLV_BASE + MFD_HIF + MFD_HIF_MSD_REG_FAST_INTERRUPT_ENABLE), PreviousState);
|
||||
#endif
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_int_register ( u_int32 dwIntID,
|
||||
PAL_PFNISR pfnHandler,
|
||||
BOOL bFIQ )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
if (pfnHandler == NULL)
|
||||
return MEDIAIP_FW_STATUS_BAD_PARAMETER;
|
||||
|
||||
if (dwIntID == PAL_IRQ_MALONE0_LOW) {
|
||||
int_handlers[INT_ID_MALONE_LOW] = pfnHandler;
|
||||
} else if (dwIntID == PAL_IRQ_MALONE0_HI) {
|
||||
int_handlers[INT_ID_MALONE_HI] = pfnHandler;
|
||||
} else {
|
||||
err_msg("wrong dwIntID 0x%x\n", dwIntID);
|
||||
return MEDIAIP_FW_STATUS_INT_NOT_HANDLED;
|
||||
}
|
||||
dprintf(LVL_FUNC, "pal pfnHandler 0x%p\n", pfnHandler);
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
MEDIAIP_FW_STATUS pal_int_enable ( u_int32 dwIntID )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
void pal_int_set ( u_int32 dwIntID )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
dprintf(LVL_FUNC, "dwIntID %d\n", dwIntID);
|
||||
|
||||
if (dwIntID != PAL_IRQ_MALONE0_LOW) {
|
||||
err_msg("ERROR: not PAL_IRQ_MALONE0_LOW!!!\n");
|
||||
EXIT_FUNC();
|
||||
return;
|
||||
}
|
||||
|
||||
VPU_REG_WR((DEC_MFD_XREG_SLV_BASE + MFD_SIF + MFD_SIF_INTR_FORCE), 0x100);
|
||||
|
||||
EXIT_FUNC();
|
||||
}
|
||||
|
||||
void pal_int_clear ( u_int32 dwIntID,
|
||||
BOOL bDirect )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_int_get_irq_line ( u_int32 uFWIrq,
|
||||
u_int32 *puIrqLine )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_memcpy ( void *pDest,
|
||||
const void *pSrc,
|
||||
u_int32 uSize )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
if (pDest == NULL || pSrc == NULL)
|
||||
return MEDIAIP_FW_STATUS_BAD_PARAMETER;
|
||||
|
||||
memcpy(pDest, pSrc, uSize);
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
void pal_memset ( void *pDest, int32 nChar, u_int32 uCount )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
dprintf(LVL_FUNC, "pDest 0x%p, nChar %d, uCount %d\n", pDest, nChar, uCount);
|
||||
if (pDest == NULL)
|
||||
return;
|
||||
|
||||
memset(pDest, nChar, uCount);
|
||||
}
|
||||
|
||||
BOOL pal_memcompare ( void *pArea1, void *pArea2, u_int32 uSizeInWords )
|
||||
{
|
||||
u_int32 i;
|
||||
u_int32 *ptr0, *ptr1;
|
||||
u_int32 uChange;
|
||||
|
||||
ENTER_FUNC();
|
||||
if (pArea1 == NULL || pArea2 == NULL)
|
||||
return FALSE;
|
||||
|
||||
ptr0 = ( u_int32 * ) pArea1;
|
||||
ptr1 = ( u_int32 * ) pArea2;
|
||||
|
||||
for ( i = 0, uChange = 0; ( i < uSizeInWords ) && ( uChange == 0 ); i++ )
|
||||
{
|
||||
if ( ptr0[i] != ptr1[i] )
|
||||
{
|
||||
uChange = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return ( uChange ) ? TRUE : FALSE;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_timer_create ( PAL_PFNTIMER pfnCallback,
|
||||
void * pUserData,
|
||||
PAL_TIMER_ID * pTimer )
|
||||
{
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_timer_destroy( PAL_TIMER_ID Timer )
|
||||
{
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: pal_memalloc //
|
||||
// //
|
||||
// DESCRIPTION: //
|
||||
// allocates size bytes and returns a pointer to the allocated memory. //
|
||||
// The memory is not cleared. //
|
||||
// //
|
||||
// INPUT PARAMETERS: //
|
||||
// uSize - Size of memory in bytes to alloc //
|
||||
// //
|
||||
// OUTPUT PARAMETERS: //
|
||||
// //
|
||||
// RETURN VALUES: //
|
||||
// //
|
||||
// NOTES: //
|
||||
// //
|
||||
// CONTEXT: //
|
||||
// This function may be called from any context //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
|
||||
void * pal_memalloc ( size_t uSize )
|
||||
{
|
||||
void * pPtr = malloc ( uSize );
|
||||
|
||||
return pPtr;
|
||||
}
|
||||
#endif
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// FUNCTION: pal_memfree //
|
||||
// //
|
||||
// DESCRIPTION: //
|
||||
// frees the memory space pointed to by ptr, which must have been //
|
||||
// returned by a previous call to malloc(), calloc() or realloc(). //
|
||||
// Otherwise, or if free(ptr) has already been called before, undefined //
|
||||
// behaviour occurs. If ptr is NULL, no operation is performed. //
|
||||
// //
|
||||
// //
|
||||
// INPUT PARAMETERS: //
|
||||
// pPtr - Pointer to memory to free //
|
||||
// //
|
||||
// OUTPUT PARAMETERS: //
|
||||
// //
|
||||
// RETURN VALUES: //
|
||||
// //
|
||||
// NOTES: //
|
||||
// //
|
||||
// CONTEXT: //
|
||||
// This function may be called from any context //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
|
||||
void pal_memfree ( void * pPtr )
|
||||
{
|
||||
free ( pPtr );
|
||||
}
|
||||
#endif
|
||||
u_int32 pal_find_highest_bit ( u_int32 uValue )
|
||||
{
|
||||
u_int32 mask = 0x80000000;
|
||||
u_int32 ret = 31;
|
||||
|
||||
ENTER_FUNC();
|
||||
|
||||
while (mask && ((uValue & mask) == 0)) {
|
||||
mask >>= 1;
|
||||
ret--;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_create ( const char * pszName,
|
||||
PAL_PERF_ID * pPCId )
|
||||
{
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_destroy ( PAL_PERF_ID PCId )
|
||||
{
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_start ( PAL_PERF_ID PCId )
|
||||
{
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_pause_control ( PAL_PERF_ID PCId , bool bStartPause)
|
||||
{
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_perf_counter_read ( PAL_PERF_ID PerfId,
|
||||
u_int32 * puCountVal )
|
||||
{
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_reg_init ( void )
|
||||
{
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
static void mfd_clock_enable(unsigned int mask, bool bEnable)
|
||||
{
|
||||
if (bEnable)
|
||||
VPU_REG_WR((DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET), mask);
|
||||
else
|
||||
VPU_REG_WR((DEC_MFD_XREG_SLV_BASE + MFD_BLK_CTRL + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_CLR), mask);
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_common ( bool bEnable )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
mfd_clock_enable(0x10, bEnable);
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_avc ( bool bEnable )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
mfd_clock_enable(0x1, bEnable);
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_vc1 ( bool bEnable )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
mfd_clock_enable(0x2, bEnable);
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_mpg ( bool bEnable )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
mfd_clock_enable(0x4, bEnable);
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_malone_clock_enable_avs ( bool bEnable )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
mfd_clock_enable(0x8, bEnable);
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
u_int32 pal_get_target_version ( void )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef VPU_KERNEL_BUILD
|
||||
MEDIAIP_FW_STATUS pal_get_phy_buf(psPALMemDesc pbuf)
|
||||
{
|
||||
vpu_mem_desc mem_desc = {0};
|
||||
int ret;
|
||||
|
||||
ENTER_FUNC();
|
||||
|
||||
mem_desc.size = pbuf->size;
|
||||
ret = IOGetPhyMem(&mem_desc);
|
||||
if (ret) {
|
||||
err_msg("Unable to obtain physical mem\n");
|
||||
return MEDIAIP_FW_STATUS_RESOURCE_ERROR;
|
||||
}
|
||||
|
||||
if (IOGetVirtMem(&mem_desc) == -1) {
|
||||
err_msg("Unable to obtain virtual mem\n");
|
||||
IOFreePhyMem(&mem_desc);
|
||||
return MEDIAIP_FW_STATUS_RESOURCE_ERROR;
|
||||
}
|
||||
|
||||
pbuf->phy_addr = mem_desc.phy_addr;
|
||||
pbuf->virt_addr = mem_desc.virt_uaddr;
|
||||
#ifdef USE_ION
|
||||
pbuf->ion_buf_fd = mem_desc.ion_buf_fd;
|
||||
#endif
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_free_phy_buf(psPALMemDesc pbuf)
|
||||
{
|
||||
vpu_mem_desc mem_desc = {0};
|
||||
|
||||
ENTER_FUNC();
|
||||
|
||||
mem_desc.size = pbuf->size;
|
||||
mem_desc.phy_addr = pbuf->phy_addr;
|
||||
mem_desc.virt_uaddr = pbuf->virt_addr;
|
||||
#ifdef USE_ION
|
||||
mem_desc.ion_buf_fd = pbuf->ion_buf_fd;
|
||||
#endif
|
||||
|
||||
IOFreeVirtMem(&mem_desc);
|
||||
IOFreePhyMem(&mem_desc);
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
u_int32 pal_va2pa ( u_int32 * pAddr )
|
||||
{
|
||||
/* CAUTION: pAddr shall be physical address already*/
|
||||
dprintf(LVL_FUNC, "pAddr 0x%p shall be physical!!!\n", pAddr);
|
||||
return (u_int32)(uint_addr)pAddr;
|
||||
}
|
||||
|
||||
u_int32 * pal_return_uncached_addr ( u_int32 * puAddress )
|
||||
{
|
||||
dprintf(LVL_FUNC, "puAddress 0x%p\n", puAddress);
|
||||
return puAddress;
|
||||
}
|
||||
|
||||
u_int32 * pal_return_cacheable_addr ( u_int32 * puAddress )
|
||||
{
|
||||
dprintf(LVL_FUNC, "puAddress 0x%p\n", puAddress);
|
||||
return puAddress;
|
||||
}
|
||||
|
||||
u_int32 pal_read_uncached ( u_int32 * puAddress )
|
||||
{
|
||||
dprintf(LVL_FUNC, "puAddress 0x%p\n", puAddress);
|
||||
|
||||
if (puAddress == NULL)
|
||||
return MEDIAIP_FW_STATUS_BAD_PARAMETER;
|
||||
|
||||
return (*puAddress);
|
||||
}
|
||||
|
||||
int pal_vsnprintf ( char *str, int size, const char *format, va_list args )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pal_sprintf ( char *str, int size, const char *psz_format, ...)
|
||||
{
|
||||
ENTER_FUNC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mfd_cache_clock_enable(unsigned int enable)
|
||||
{
|
||||
ENTER_FUNC();
|
||||
VPU_REG_WR((SCB_XREG_SLV_BASE + SCB_SCB_BLK_CTRL + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET),enable);
|
||||
}
|
||||
|
||||
void pal_set_malone_cache ( u_int32 uMalID )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
mfd_cache_clock_enable(0xE);
|
||||
}
|
||||
|
||||
#define MAX_QUEUE_NUM 10
|
||||
static PAL_QUEUE_ID gQuId = 0;
|
||||
|
||||
MEDIAIP_FW_STATUS pal_sem_create ( u_int32 uInitialValue,
|
||||
const char *pszName,
|
||||
PAL_SEM_ID *pSem)
|
||||
{
|
||||
/* CAUTION: if in use */
|
||||
ENTER_FUNC();
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
#ifdef VPU_KERNEL_BUILD
|
||||
|
||||
static struct kfifo irq_fifo[MAX_QUEUE_NUM];
|
||||
static spinlock_t irq_lock[MAX_QUEUE_NUM];
|
||||
static struct task_struct *msg_thread;
|
||||
static wait_queue_head_t irq_wq[MAX_QUEUE_NUM];
|
||||
|
||||
MEDIAIP_FW_STATUS pal_thread_create ( PAL_PFNTHREAD pfnEntryPoint,
|
||||
int nArgC,
|
||||
void **ppArgV,
|
||||
u_int32 uStackSize,
|
||||
u_int8 uPrio,
|
||||
const char *pszName,
|
||||
PAL_THREAD_ID *pId )
|
||||
{
|
||||
typedef int (*INTFUNC)(void *);
|
||||
|
||||
/* CAUTION: shall not enter twice due to global msg_thread */
|
||||
ENTER_FUNC();
|
||||
//struct task_struct *msg_thread;
|
||||
msg_thread = kthread_run((INTFUNC)pfnEntryPoint , NULL, pszName);
|
||||
if(IS_ERR( msg_thread ))
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_thread_terminate ( PAL_THREAD_ID *pId )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
|
||||
kthread_stop(msg_thread);
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_create ( unsigned int nMaxElements,
|
||||
const char *pszName,
|
||||
PAL_QUEUE_ID *pQuId )
|
||||
{
|
||||
/* CAUTION: message length shall be 4 * sizeof(uint_addr) */
|
||||
ENTER_FUNC();
|
||||
*pQuId = gQuId;
|
||||
spin_lock_init(&irq_lock[*pQuId]);
|
||||
init_waitqueue_head(&irq_wq[*pQuId]);
|
||||
if(kfifo_alloc(&irq_fifo[*pQuId],
|
||||
nMaxElements * 4 * sizeof(uint_addr),
|
||||
GFP_KERNEL))
|
||||
{
|
||||
err_msg("fail to alloc fifo in pal\n");
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
}
|
||||
|
||||
gQuId++;
|
||||
if( MAX_QUEUE_NUM == gQuId)
|
||||
gQuId=0;
|
||||
dprintf(LVL_FUNC, "create QuId:%d\n",
|
||||
*pQuId
|
||||
);
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_destroy ( PAL_QUEUE_ID QuId )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
dprintf(LVL_FUNC, "destory QuId:%d\n",
|
||||
QuId
|
||||
);
|
||||
kfifo_free(&irq_fifo[QuId]);
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_send ( PAL_QUEUE_ID QuId,
|
||||
void *pMessage)
|
||||
{
|
||||
u_int32 retval;
|
||||
ENTER_FUNC();
|
||||
dprintf(LVL_FUNC, "QuId %d\n", QuId);
|
||||
|
||||
/* CAUTION: if message is not 4 * sizeof(uint_addr) */
|
||||
retval = kfifo_in_locked(&irq_fifo[QuId], pMessage, 4 * sizeof(uint_addr),&irq_lock[QuId]);
|
||||
dprintf(LVL_FUNC, "message send: 0x%llx, 0x%llx, 0x%llx, 0x%llx\n", *(uint_addr *)pMessage, *((uint_addr *)pMessage+1), *((uint_addr *)pMessage+2), *((uint_addr *)pMessage+3));
|
||||
if(retval != 4*sizeof(uint_addr))
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
wake_up(&irq_wq[QuId]);
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_receive ( PAL_QUEUE_ID QuId,
|
||||
u_int32 uTimeoutMs,
|
||||
void *pMessage )
|
||||
{
|
||||
u_int32 retval;
|
||||
|
||||
ENTER_FUNC();
|
||||
dprintf(LVL_FUNC, "QuId %d\n", QuId);
|
||||
/* while (kfifo_len(&irq_fifo) < sizeof(*pMessage)) {
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
schedule();
|
||||
}*/
|
||||
if(!wait_event_interruptible_timeout(irq_wq[QuId],
|
||||
kfifo_len(&irq_fifo[QuId])>=4*sizeof(uint_addr)
|
||||
/* || kthread_should_stop() */,
|
||||
//uTimeoutMs
|
||||
msecs_to_jiffies(uTimeoutMs)
|
||||
))
|
||||
{
|
||||
dprintf(LVL_FUNC, "timeout %d ms\n", uTimeoutMs);
|
||||
return MEDIAIP_FW_STATUS_TIMEOUT;
|
||||
}
|
||||
//if(kthread_should_stop())
|
||||
// return MEDIAIP_FW_STATUS_STOPPED;
|
||||
|
||||
if (kfifo_len(&irq_fifo[QuId])>=4*sizeof(uint_addr))
|
||||
{
|
||||
retval = kfifo_out_locked(&irq_fifo[QuId], pMessage, 4*sizeof(uint_addr),&irq_lock[QuId]);
|
||||
dprintf(LVL_FUNC, "message receive: 0x%llx, 0x%llx, 0x%llx, 0x%llx\n", *(uint_addr *)pMessage, *((uint_addr *)pMessage+1), *((uint_addr *)pMessage+2), *((uint_addr *)pMessage+3));
|
||||
}
|
||||
else
|
||||
{
|
||||
dprintf(LVL_FUNC, "ERROR interrupted by a signal!!\n");
|
||||
}
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define FN_MSG_FIFO "/dev/shm/vpu_msg_fifo"
|
||||
static char fn_fifo[MAX_QUEUE_NUM][64] = {0};
|
||||
static int fd_send[MAX_QUEUE_NUM] = {0};
|
||||
static int fd_receive[MAX_QUEUE_NUM] = {0};
|
||||
|
||||
MEDIAIP_FW_STATUS pal_thread_create ( PAL_PFNTHREAD pfnEntryPoint,
|
||||
int nArgC,
|
||||
void **ppArgV,
|
||||
u_int32 uStackSize,
|
||||
u_int8 uPrio,
|
||||
const char *pszName,
|
||||
PAL_THREAD_ID *pId )
|
||||
{
|
||||
int err;
|
||||
pthread_t msg_tid;
|
||||
|
||||
ENTER_FUNC();
|
||||
err = pthread_create(&msg_tid, NULL, (void *)pfnEntryPoint, NULL);
|
||||
if (err)
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
|
||||
*pId = msg_tid;
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_thread_terminate ( PAL_THREAD_ID *pId )
|
||||
{
|
||||
pthread_t msg_tid = *pId;
|
||||
|
||||
ENTER_FUNC();
|
||||
|
||||
if (msg_tid == 0)
|
||||
return MEDIAIP_FW_STATUS_BAD_PARAMETER;
|
||||
|
||||
pthread_cancel(msg_tid);
|
||||
pthread_join(msg_tid, NULL);
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_create ( unsigned int nMaxElements,
|
||||
const char *pszName,
|
||||
PAL_QUEUE_ID *pQuId )
|
||||
{
|
||||
/* CAUTION: message length shall be 4 * sizeof(uint_addr) */
|
||||
ENTER_FUNC();
|
||||
*pQuId = gQuId;
|
||||
sprintf(fn_fifo[gQuId], "%s%d", FN_MSG_FIFO, gQuId);
|
||||
if(access(fn_fifo[gQuId], F_OK) == -1)
|
||||
{
|
||||
if(mkfifo(fn_fifo[gQuId], 0777))
|
||||
{
|
||||
err_msg("failed to alloc fifo %s in pal\n", fn_fifo[gQuId]);
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
}
|
||||
dprintf(LVL_FUNC, "created fifo %s\n", fn_fifo[gQuId]);
|
||||
} else {
|
||||
dprintf(LVL_FUNC, "exist fifo %s\n", fn_fifo[gQuId]);
|
||||
}
|
||||
|
||||
gQuId++;
|
||||
if( MAX_QUEUE_NUM == gQuId)
|
||||
gQuId=0;
|
||||
dprintf(LVL_FUNC, "create QuId:%d\n",
|
||||
*pQuId
|
||||
);
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_destroy ( PAL_QUEUE_ID QuId )
|
||||
{
|
||||
ENTER_FUNC();
|
||||
dprintf(LVL_FUNC, "destory QuId:%d\n",
|
||||
QuId
|
||||
);
|
||||
if (fd_send[QuId]) {
|
||||
close(fd_send[QuId]);
|
||||
fd_send[QuId] = 0;
|
||||
}
|
||||
if (fd_receive[QuId]) {
|
||||
close(fd_receive[QuId]);
|
||||
fd_receive[QuId] = 0;
|
||||
}
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_send ( PAL_QUEUE_ID QuId,
|
||||
void *pMessage)
|
||||
{
|
||||
u_int32 retval;
|
||||
ENTER_FUNC();
|
||||
dprintf(LVL_FUNC, "QuId %d\n", QuId);
|
||||
|
||||
/* CAUTION: if message is not 4 * sizeof(uint_addr) */
|
||||
if (fd_send[QuId] == 0) {
|
||||
fd_send[QuId] = open(fn_fifo[QuId], O_WRONLY);
|
||||
if (fd_send[QuId] == -1) {
|
||||
err_msg("failed to open fifo %s to send\n", fn_fifo[QuId]);
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
} else {
|
||||
dprintf(LVL_FUNC, "opened fifo %s to send\n", fn_fifo[QuId]);
|
||||
}
|
||||
}
|
||||
retval = write(fd_send[QuId], pMessage, 4 * sizeof(uint_addr));
|
||||
if(retval != 4*sizeof(uint_addr))
|
||||
{
|
||||
err_msg("%s\n", strerror(errno));
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
}
|
||||
dprintf(LVL_FUNC, "message send: 0x%lx, 0x%lx, 0x%lx, 0x%lx\n", *(uint_addr *)pMessage, *((uint_addr *)pMessage+1), *((uint_addr *)pMessage+2), *((uint_addr *)pMessage+3));
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
|
||||
MEDIAIP_FW_STATUS pal_qu_receive ( PAL_QUEUE_ID QuId,
|
||||
u_int32 uTimeoutMs,
|
||||
void *pMessage )
|
||||
{
|
||||
u_int32 retval;
|
||||
|
||||
ENTER_FUNC();
|
||||
dprintf(LVL_FUNC, "QuId %d\n", QuId);
|
||||
// TODO: time out case
|
||||
if (fd_receive[QuId] == 0) {
|
||||
fd_receive[QuId] = open(fn_fifo[QuId], O_RDONLY);
|
||||
if (fd_receive[QuId] == -1) {
|
||||
err_msg("failed to open fifo %s to receive\n", fn_fifo[QuId]);
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
} else {
|
||||
dprintf(LVL_FUNC, "opened fifo %s to receive\n", fn_fifo[QuId]);
|
||||
}
|
||||
}
|
||||
retval = read(fd_receive[QuId], pMessage, 4*sizeof(uint_addr));
|
||||
if(retval != 4*sizeof(uint_addr))
|
||||
{
|
||||
err_msg("%s\n", strerror(errno));
|
||||
return MEDIAIP_FW_STATUS_FAILURE;
|
||||
}
|
||||
dprintf(LVL_FUNC, "message receive: 0x%lx, 0x%lx, 0x%lx, 0x%lx\n", *(uint_addr *)pMessage, *((uint_addr *)pMessage+1), *((uint_addr *)pMessage+2), *((uint_addr *)pMessage+3));
|
||||
|
||||
return MEDIAIP_FW_STATUS_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU Lesser General
|
||||
* Public License. You may obtain a copy of the GNU Lesser General
|
||||
* Public License Version 2.1 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/lgpl-license.html
|
||||
* http://www.gnu.org/copyleft/lgpl.html
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file vpu_debug.h
|
||||
*
|
||||
* @brief VPU debug definition
|
||||
*
|
||||
* @ingroup VPU
|
||||
*/
|
||||
|
||||
#ifndef __VPU_DEBUG_H
|
||||
#define __VPU_DEBUG_H
|
||||
|
||||
|
||||
|
||||
#define LVL_NOPRINT 0
|
||||
#define LVL_ISR 2
|
||||
#define LVL_CRI 3
|
||||
#define LVL_FUNC 5
|
||||
#define LVL_PRINTALL 10
|
||||
|
||||
|
||||
|
||||
#ifdef VPU_KERNEL_BUILD
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
//#define vpu_lib_dbg_level LVL_PRINTALL
|
||||
|
||||
#define vpu_lib_dbg_level LVL_NOPRINT
|
||||
|
||||
#define err_msg(fmt, arg...) do { if (vpu_lib_dbg_level > LVL_NOPRINT) \
|
||||
printk("[ERR]\t%s:%d " fmt, __FILE__, __LINE__, ## arg); else \
|
||||
printk("[ERR]\t" fmt, ## arg); \
|
||||
} while (0)
|
||||
#define info_msg(fmt, arg...) do { if (vpu_lib_dbg_level > LVL_NOPRINT) \
|
||||
printk("[INFO]\t%s:%d " fmt, __FILE__, __LINE__, ## arg); else \
|
||||
printk("[INFO]\t" fmt, ## arg); \
|
||||
} while (0)
|
||||
#define warn_msg(fmt, arg...) do { if (vpu_lib_dbg_level > LVL_NOPRINT) \
|
||||
printk("[WARN]\t%s:%d " fmt, __FILE__, __LINE__, ## arg); else \
|
||||
printk("[WARN]\t" fmt, ## arg); \
|
||||
} while (0)
|
||||
|
||||
#define dprintf(level, fmt, arg...) do {if (level <= vpu_lib_dbg_level) printk("[DEBUG]\t%s " fmt, __FUNCTION__, ## arg);} while(0)
|
||||
|
||||
|
||||
|
||||
#define ENTER_FUNC() dprintf(LVL_FUNC, "enter %s()\n", __func__)
|
||||
#define EXIT_FUNC() dprintf(LVL_FUNC, "exit %s()\n", __func__)
|
||||
|
||||
#else
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "VPU_lib.h"
|
||||
|
||||
|
||||
//#define vpu_lib_dbg_level LVL_PRINTALL
|
||||
|
||||
#define vpu_lib_dbg_level LVL_CRI
|
||||
|
||||
#define err_msg(fmt, arg...) do { if (vpu_lib_dbg_level > LVL_NOPRINT) \
|
||||
printf("[ERR]\t%s:%d " fmt, __FILE__, __LINE__, ## arg); else \
|
||||
printf("[ERR]\t" fmt, ## arg); \
|
||||
} while (0)
|
||||
#define info_msg(fmt, arg...) do { if (vpu_lib_dbg_level > LVL_NOPRINT) \
|
||||
printf("[INFO]\t%s:%d " fmt, __FILE__, __LINE__, ## arg); else \
|
||||
printf("[INFO]\t" fmt, ## arg); \
|
||||
} while (0)
|
||||
#define warn_msg(fmt, arg...) do { if (vpu_lib_dbg_level > LVL_NOPRINT) \
|
||||
printf("[WARN]\t%s:%d " fmt, __FILE__, __LINE__, ## arg); else \
|
||||
printf("[WARN]\t" fmt, ## arg); \
|
||||
} while (0)
|
||||
|
||||
//#define dprintf(level, fmt, arg...) do {if (level <= vpu_lib_dbg_level) printf("[DEBUG]\t%s " fmt, __FUNCTION__, ## arg);} while(0)
|
||||
#define dprintf(level, fmt, arg...) do { if (vpu_lib_dbg_level >= level) printf("[DEBUG]\t%s:%d " fmt, __FILE__, __LINE__, ## arg); } while (0)
|
||||
|
||||
#define ENTER_FUNC() dprintf(LVL_FUNC, "enter %s()\n", __func__)
|
||||
#define EXIT_FUNC() dprintf(LVL_FUNC, "exit %s()\n", __func__)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright 2017 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// vpu_regdef.h
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Register definition
|
||||
//
|
||||
// Authors:
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef __VPU_REGDEF_H__
|
||||
#define __VPU_REGDEF_H__
|
||||
|
||||
#define SCB_XREG_SLV_BASE 0x00000000
|
||||
#define SCB_SCB_BLK_CTRL 0x00070000
|
||||
#define SCB_BLK_CTRL_XMEM_RESET_SET 0x00000090
|
||||
#define SCB_BLK_CTRL_CACHE_RESET_SET 0x000000A0
|
||||
#define SCB_BLK_CTRL_CACHE_RESET_CLR 0x000000A4
|
||||
#define SCB_BLK_CTRL_SCB_CLK_ENABLE_SET 0x00000100
|
||||
|
||||
#define XMEM_CONTROL 0x00041000
|
||||
|
||||
#define DEC_MFD_XREG_SLV_BASE 0x00180000
|
||||
|
||||
#define MFD_HIF 0x0001C000
|
||||
#define MFD_HIF_MSD_REG_HOST_INTERRUPT_ENABLE 0x00000014
|
||||
#define MFD_HIF_MSD_REG_INTERRUPT_STATUS 0x00000018
|
||||
#define MFD_HIF_MSD_REG_FAST_INTERRUPT_ENABLE 0x0000001C
|
||||
#define MFD_SIF 0x0001D000
|
||||
#define MFD_SIF_CTRL_STATUS 0x000000F0
|
||||
#define MFD_SIF_INTR_STATUS 0x000000F4
|
||||
#define MFD_SIF_INTR_FORCE 0x000000F8
|
||||
#define MFD_MCX 0x00020800
|
||||
|
||||
#define MFD_BLK_CTRL 0x00030000
|
||||
#define MFD_BLK_CTRL_MFD_SYS_RESET_SET 0x00000000
|
||||
#define MFD_BLK_CTRL_MFD_SYS_RESET_CLR 0x00000004
|
||||
#define MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET 0x00000100
|
||||
#define MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_CLR 0x00000104
|
||||
|
||||
#endif //__VPU_REGDEF_H__
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU Lesser General
|
||||
* Public License. You may obtain a copy of the GNU Lesser General
|
||||
* Public License Version 2.1 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/lgpl-license.html
|
||||
* http://www.gnu.org/copyleft/lgpl.html
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @defgroup VPU Video Processor Unit Driver
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file linux/mxc_vpu-malone.h
|
||||
*
|
||||
* @brief VPU system initialization and file operation definition
|
||||
*
|
||||
* @ingroup VPU
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MXC_VPU_MALONE_H__
|
||||
#define __LINUX_MXC_VPU_MALONE_H__
|
||||
|
||||
#include <linux/fs.h>
|
||||
|
||||
struct vpu_mem_desc {
|
||||
u32 size;
|
||||
dma_addr_t phy_addr;
|
||||
void *cpu_addr; /* cpu address to free the dma mem */
|
||||
u64 virt_uaddr; /* virtual user space address */
|
||||
};
|
||||
|
||||
#define VPU_IOC_MAGIC 'V'
|
||||
|
||||
#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0)
|
||||
#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1)
|
||||
#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2)
|
||||
#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 3)
|
||||
#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 4)
|
||||
#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 5)
|
||||
#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 6)
|
||||
#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 7)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue