atheros/ath9k: add common read/write ops and port ath9k to use it
In an effort to make hw code driver core agnostic read and write operations are defined on the ath_common structure. This patch adds that and makes ath9k use it. This allows drivers like ath9k_htc to define its own read/write ops and still rely on the same hw code. This also paves the way for sharing code between ath9k/ath5k/ath9k_htc. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -39,6 +39,11 @@ struct ath_regulatory {
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struct reg_dmn_pair_mapping *regpair;
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struct reg_dmn_pair_mapping *regpair;
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};
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};
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struct ath_ops {
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unsigned int (*read)(void *, u32 reg_offset);
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void (*write)(void *, u32 val, u32 reg_offset);
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};
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struct ath_common {
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struct ath_common {
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u16 cachelsz;
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u16 cachelsz;
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u16 curaid;
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u16 curaid;
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@ -46,6 +51,7 @@ struct ath_common {
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u8 curbssid[ETH_ALEN];
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u8 curbssid[ETH_ALEN];
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u8 bssidmask[ETH_ALEN];
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u8 bssidmask[ETH_ALEN];
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struct ath_regulatory regulatory;
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struct ath_regulatory regulatory;
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struct ath_ops *ops;
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};
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};
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struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
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struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
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@ -646,16 +646,6 @@ int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
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int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
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int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
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int ath_cabq_update(struct ath_softc *);
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int ath_cabq_update(struct ath_softc *);
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static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
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{
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return &ah->common;
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}
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static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
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{
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return &(ath9k_hw_common(ah)->regulatory);
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}
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static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
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static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
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{
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{
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sc->bus_ops->read_cachesize(sc, csz);
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sc->bus_ops->read_cachesize(sc, csz);
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@ -718,8 +708,5 @@ bool ath9k_wiphy_scanning(struct ath_softc *sc);
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void ath9k_wiphy_work(struct work_struct *work);
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void ath9k_wiphy_work(struct work_struct *work);
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bool ath9k_all_wiphys_idle(struct ath_softc *sc);
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bool ath9k_all_wiphys_idle(struct ath_softc *sc);
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void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val);
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unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset);
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int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
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int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
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#endif /* ATH9K_H */
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#endif /* ATH9K_H */
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@ -81,38 +81,6 @@ static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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return ath9k_hw_mac_clks(ah, usecs);
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return ath9k_hw_mac_clks(ah, usecs);
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}
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}
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/*
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* Read and write, they both share the same lock. We do this to serialize
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* reads and writes on Atheros 802.11n PCI devices only. This is required
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* as the FIFO on these devices can only accept sanely 2 requests. After
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* that the device goes bananas. Serializing the reads/writes prevents this
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* from happening.
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*/
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void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
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{
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if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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unsigned long flags;
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spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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iowrite32(val, ah->ah_sc->mem + reg_offset);
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spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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} else
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iowrite32(val, ah->ah_sc->mem + reg_offset);
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}
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unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
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{
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u32 val;
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if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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unsigned long flags;
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spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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val = ioread32(ah->ah_sc->mem + reg_offset);
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spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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} else
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val = ioread32(ah->ah_sc->mem + reg_offset);
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return val;
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}
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
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{
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int i;
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int i;
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@ -51,8 +51,11 @@
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#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
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#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
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/* Register read/write primitives */
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/* Register read/write primitives */
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#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
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#define REG_WRITE(_ah, _reg, _val) \
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#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
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ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
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#define REG_READ(_ah, _reg) \
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ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
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#define SM(_v, _f) (((_v) << _f##_S) & _f)
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#define SM(_v, _f) (((_v) << _f##_S) & _f)
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#define MS(_v, _f) (((_v) & _f) >> _f##_S)
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#define MS(_v, _f) (((_v) & _f) >> _f##_S)
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@ -588,6 +591,16 @@ struct ath_hw {
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struct ath_gen_timer_table hw_gen_timers;
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struct ath_gen_timer_table hw_gen_timers;
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};
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};
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static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
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{
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return &ah->common;
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}
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static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
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{
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return &(ath9k_hw_common(ah)->regulatory);
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}
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/* Initialization, Detach, Reset */
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/* Initialization, Detach, Reset */
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const char *ath9k_hw_probe(u16 vendorid, u16 devid);
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const char *ath9k_hw_probe(u16 vendorid, u16 devid);
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void ath9k_hw_detach(struct ath_hw *ah);
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void ath9k_hw_detach(struct ath_hw *ah);
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@ -1489,6 +1489,47 @@ static int ath_init_btcoex_timer(struct ath_softc *sc)
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return 0;
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return 0;
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}
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}
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/*
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* Read and write, they both share the same lock. We do this to serialize
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* reads and writes on Atheros 802.11n PCI devices only. This is required
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* as the FIFO on these devices can only accept sanely 2 requests. After
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* that the device goes bananas. Serializing the reads/writes prevents this
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* from happening.
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*/
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static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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unsigned long flags;
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spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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iowrite32(val, ah->ah_sc->mem + reg_offset);
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spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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} else
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iowrite32(val, ah->ah_sc->mem + reg_offset);
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}
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static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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u32 val;
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if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
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unsigned long flags;
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spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
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val = ioread32(ah->ah_sc->mem + reg_offset);
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spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
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} else
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val = ioread32(ah->ah_sc->mem + reg_offset);
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return val;
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}
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static struct ath_ops ath9k_common_ops = {
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.read = ath9k_ioread32,
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.write = ath9k_iowrite32,
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};
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/*
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/*
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* Initialize and fill ath_softc, ath_sofct is the
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* Initialize and fill ath_softc, ath_sofct is the
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* "Software Carrier" struct. Historically it has existed
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* "Software Carrier" struct. Historically it has existed
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@ -1528,6 +1569,7 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
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sc->sc_ah = ah;
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sc->sc_ah = ah;
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common = ath9k_hw_common(ah);
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common = ath9k_hw_common(ah);
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common->ops = &ath9k_common_ops;
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/*
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/*
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* Cache line size is used to size and align various
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* Cache line size is used to size and align various
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