[TG3]: Enable auto MDI.
This patch adds automatic MDI crossover support when autonegotiation is turned off. Automatic MDI crossover allows link to be established without the use of a crossover cable. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -721,6 +721,44 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
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return ret;
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}
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static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
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{
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u32 phy;
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
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(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
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return;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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u32 ephy;
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if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
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tg3_writephy(tp, MII_TG3_EPHY_TEST,
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ephy | MII_TG3_EPHY_SHADOW_EN);
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if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
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if (enable)
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phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
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else
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phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
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tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
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}
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tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
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}
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} else {
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phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
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MII_TG3_AUXCTL_SHDWSEL_MISC;
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if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
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!tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
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if (enable)
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phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
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else
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phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
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phy |= MII_TG3_AUXCTL_MISC_WREN;
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tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
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}
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}
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}
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static void tg3_phy_set_wirespeed(struct tg3 *tp)
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{
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u32 val;
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@ -1045,23 +1083,11 @@ out:
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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u32 phy_reg;
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/* adjust output voltage */
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tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
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if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
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u32 phy_reg2;
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tg3_writephy(tp, MII_TG3_EPHY_TEST,
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phy_reg | MII_TG3_EPHY_SHADOW_EN);
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/* Enable auto-MDIX */
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if (!tg3_readphy(tp, 0x10, &phy_reg2))
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tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
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tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
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}
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}
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tg3_phy_toggle_automdix(tp, 1);
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tg3_phy_set_wirespeed(tp);
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return 0;
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}
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@ -8847,14 +8873,14 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
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phytest | MII_TG3_EPHY_SHADOW_EN);
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if (!tg3_readphy(tp, 0x1b, &phy))
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tg3_writephy(tp, 0x1b, phy & ~0x20);
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if (!tg3_readphy(tp, 0x10, &phy))
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tg3_writephy(tp, 0x10, phy & ~0x4000);
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tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
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}
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val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
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} else
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val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
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tg3_phy_toggle_automdix(tp, 0);
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tg3_writephy(tp, MII_BMCR, val);
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udelay(40);
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@ -1642,6 +1642,11 @@
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#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
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#define MII_TG3_AUXCTL_MISC_WREN 0x8000
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#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
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#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
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#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
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#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
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#define MII_TG3_AUX_STAT_LPASS 0x0004
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#define MII_TG3_AUX_STAT_SPDMASK 0x0700
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@ -1667,6 +1672,9 @@
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#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
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#define MII_TG3_EPHY_SHADOW_EN 0x80
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#define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */
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#define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000
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#define MII_TG3_TEST1 0x1e
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#define MII_TG3_TEST1_TRIM_EN 0x0010
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#define MII_TG3_TEST1_CRC_EN 0x8000
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