iommu/vt-d: Cleanup log messages
Give them a common prefix that can be grepped for and improve the wording here and there. Tested-by: ZhenHua Li <zhen-hual@hp.com> Tested-by: Baoquan He <bhe@redhat.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
parent
0f57d86787
commit
9f10e5bf62
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@ -26,7 +26,7 @@
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* These routines are used by both DMA-remapping and Interrupt-remapping
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt /* has to precede printk.h */
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#define pr_fmt(fmt) "DMAR: " fmt
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#include <linux/pci.h>
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#include <linux/dmar.h>
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@ -555,7 +555,7 @@ static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
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break;
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} else if (next > end) {
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/* Avoid passing table end */
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pr_warn(FW_BUG "record passes table end\n");
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pr_warn(FW_BUG "Record passes table end\n");
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ret = -EINVAL;
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break;
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}
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@ -802,7 +802,7 @@ int __init dmar_table_init(void)
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ret = parse_dmar_table();
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if (ret < 0) {
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if (ret != -ENODEV)
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pr_info("parse DMAR table failure.\n");
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pr_info("Parse DMAR table failure.\n");
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} else if (list_empty(&dmar_drhd_units)) {
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pr_info("No DMAR devices found\n");
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ret = -ENODEV;
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@ -847,7 +847,7 @@ dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
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else
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addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
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if (!addr) {
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pr_warn("IOMMU: can't validate: %llx\n", drhd->address);
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pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
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return -EINVAL;
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}
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@ -921,14 +921,14 @@ static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
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iommu->reg_size = VTD_PAGE_SIZE;
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if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
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pr_err("IOMMU: can't reserve memory\n");
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pr_err("Can't reserve memory\n");
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err = -EBUSY;
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goto out;
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}
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iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
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if (!iommu->reg) {
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pr_err("IOMMU: can't map the region\n");
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pr_err("Can't map the region\n");
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err = -ENOMEM;
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goto release;
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}
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@ -952,13 +952,13 @@ static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
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iommu->reg_size = map_size;
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if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
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iommu->name)) {
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pr_err("IOMMU: can't reserve memory\n");
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pr_err("Can't reserve memory\n");
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err = -EBUSY;
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goto out;
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}
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iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
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if (!iommu->reg) {
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pr_err("IOMMU: can't map the region\n");
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pr_err("Can't map the region\n");
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err = -ENOMEM;
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goto release;
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}
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@ -1014,14 +1014,14 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd)
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return -ENOMEM;
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if (dmar_alloc_seq_id(iommu) < 0) {
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pr_err("IOMMU: failed to allocate seq_id\n");
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pr_err("Failed to allocate seq_id\n");
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err = -ENOSPC;
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goto error;
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}
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err = map_iommu(iommu, drhd->reg_base_addr);
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if (err) {
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pr_err("IOMMU: failed to map %s\n", iommu->name);
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pr_err("Failed to map %s\n", iommu->name);
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goto error_free_seq_id;
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}
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@ -1045,8 +1045,8 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd)
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iommu->node = -1;
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ver = readl(iommu->reg + DMAR_VER_REG);
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pr_info("IOMMU %d: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
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iommu->seq_id,
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pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
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iommu->name,
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(unsigned long long)drhd->reg_base_addr,
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DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
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(unsigned long long)iommu->cap,
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@ -1644,7 +1644,7 @@ int dmar_set_interrupt(struct intel_iommu *iommu)
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irq = dmar_alloc_hwirq();
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if (irq <= 0) {
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pr_err("IOMMU: no free vectors\n");
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pr_err("No free IRQ vectors\n");
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return -EINVAL;
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}
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@ -1661,7 +1661,7 @@ int dmar_set_interrupt(struct intel_iommu *iommu)
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ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
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if (ret)
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pr_err("IOMMU: can't request irq\n");
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pr_err("Can't request irq\n");
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return ret;
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}
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@ -15,8 +15,11 @@
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* Shaohua Li <shaohua.li@intel.com>,
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* Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
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* Fenghua Yu <fenghua.yu@intel.com>
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* Joerg Roedel <jroedel@suse.de>
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*/
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#define pr_fmt(fmt) "DMAR: " fmt
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#include <linux/init.h>
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#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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@ -453,25 +456,21 @@ static int __init intel_iommu_setup(char *str)
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while (*str) {
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if (!strncmp(str, "on", 2)) {
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dmar_disabled = 0;
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printk(KERN_INFO "Intel-IOMMU: enabled\n");
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pr_info("IOMMU enabled\n");
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} else if (!strncmp(str, "off", 3)) {
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dmar_disabled = 1;
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printk(KERN_INFO "Intel-IOMMU: disabled\n");
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pr_info("IOMMU disabled\n");
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} else if (!strncmp(str, "igfx_off", 8)) {
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dmar_map_gfx = 0;
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printk(KERN_INFO
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"Intel-IOMMU: disable GFX device mapping\n");
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pr_info("Disable GFX device mapping\n");
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} else if (!strncmp(str, "forcedac", 8)) {
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printk(KERN_INFO
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"Intel-IOMMU: Forcing DAC for PCI devices\n");
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pr_info("Forcing DAC for PCI devices\n");
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dmar_forcedac = 1;
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} else if (!strncmp(str, "strict", 6)) {
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printk(KERN_INFO
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"Intel-IOMMU: disable batched IOTLB flush\n");
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pr_info("Disable batched IOTLB flush\n");
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intel_iommu_strict = 1;
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} else if (!strncmp(str, "sp_off", 6)) {
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printk(KERN_INFO
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"Intel-IOMMU: disable supported super page\n");
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pr_info("Disable supported super page\n");
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intel_iommu_superpage = 0;
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} else if (!strncmp(str, "ecs_off", 7)) {
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printk(KERN_INFO
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@ -1132,7 +1131,7 @@ static int iommu_alloc_root_entry(struct intel_iommu *iommu)
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root = (struct root_entry *)alloc_pgtable_page(iommu->node);
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if (!root) {
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pr_err("IOMMU: allocating root entry for %s failed\n",
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pr_err("Allocating root entry for %s failed\n",
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iommu->name);
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return -ENOMEM;
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}
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@ -1270,9 +1269,9 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
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/* check IOTLB invalidation granularity */
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if (DMA_TLB_IAIG(val) == 0)
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printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
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pr_err("Flush IOTLB failed\n");
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if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
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pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
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pr_debug("TLB flush request %Lx, actual %Lx\n",
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(unsigned long long)DMA_TLB_IIRG(type),
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(unsigned long long)DMA_TLB_IAIG(val));
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}
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@ -1443,8 +1442,8 @@ static int iommu_init_domains(struct intel_iommu *iommu)
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unsigned long nlongs;
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ndomains = cap_ndoms(iommu->cap);
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pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
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iommu->seq_id, ndomains);
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pr_debug("%s: Number of Domains supported <%ld>\n",
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iommu->name, ndomains);
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nlongs = BITS_TO_LONGS(ndomains);
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spin_lock_init(&iommu->lock);
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@ -1454,15 +1453,15 @@ static int iommu_init_domains(struct intel_iommu *iommu)
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*/
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iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
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if (!iommu->domain_ids) {
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pr_err("IOMMU%d: allocating domain id array failed\n",
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iommu->seq_id);
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pr_err("%s: Allocating domain id array failed\n",
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iommu->name);
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return -ENOMEM;
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}
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iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
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GFP_KERNEL);
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if (!iommu->domains) {
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pr_err("IOMMU%d: allocating domain array failed\n",
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iommu->seq_id);
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pr_err("%s: Allocating domain array failed\n",
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iommu->name);
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kfree(iommu->domain_ids);
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iommu->domain_ids = NULL;
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return -ENOMEM;
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@ -1567,7 +1566,7 @@ static int iommu_attach_domain(struct dmar_domain *domain,
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num = __iommu_attach_domain(domain, iommu);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (num < 0)
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pr_err("IOMMU: no free domain ids\n");
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pr_err("%s: No free domain ids\n", iommu->name);
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return num;
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}
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@ -1659,7 +1658,7 @@ static int dmar_init_reserved_ranges(void)
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iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
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IOVA_PFN(IOAPIC_RANGE_END));
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if (!iova) {
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printk(KERN_ERR "Reserve IOAPIC range failed\n");
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pr_err("Reserve IOAPIC range failed\n");
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return -ENODEV;
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}
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@ -1675,7 +1674,7 @@ static int dmar_init_reserved_ranges(void)
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IOVA_PFN(r->start),
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IOVA_PFN(r->end));
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if (!iova) {
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printk(KERN_ERR "Reserve iova failed\n");
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pr_err("Reserve iova failed\n");
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return -ENODEV;
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}
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}
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@ -1722,7 +1721,7 @@ static int domain_init(struct dmar_domain *domain, int guest_width)
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sagaw = cap_sagaw(iommu->cap);
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if (!test_bit(agaw, &sagaw)) {
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/* hardware doesn't support it, choose a bigger one */
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pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
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pr_debug("Hardware doesn't support agaw %d\n", agaw);
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agaw = find_next_bit(&sagaw, 5, agaw);
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if (agaw >= 5)
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return -ENODEV;
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@ -1823,7 +1822,7 @@ static int domain_context_mapping_one(struct dmar_domain *domain,
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id = iommu_attach_vm_domain(domain, iommu);
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if (id < 0) {
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spin_unlock_irqrestore(&iommu->lock, flags);
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pr_err("IOMMU: no free domain ids\n");
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pr_err("%s: No free domain ids\n", iommu->name);
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return -EFAULT;
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}
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}
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@ -2050,8 +2049,8 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
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if (tmp) {
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static int dumps = 5;
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printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
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iov_pfn, tmp, (unsigned long long)pteval);
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pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
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iov_pfn, tmp, (unsigned long long)pteval);
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if (dumps) {
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dumps--;
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debug_dma_dump_mappings(NULL);
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@ -2323,7 +2322,7 @@ static int iommu_domain_identity_map(struct dmar_domain *domain,
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if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
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dma_to_mm_pfn(last_vpfn))) {
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printk(KERN_ERR "IOMMU: reserve iova failed\n");
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pr_err("Reserving iova failed\n");
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return -ENOMEM;
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}
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@ -2356,15 +2355,14 @@ static int iommu_prepare_identity_map(struct device *dev,
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range which is reserved in E820, so which didn't get set
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up to start with in si_domain */
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if (domain == si_domain && hw_pass_through) {
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printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
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dev_name(dev), start, end);
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pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
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dev_name(dev), start, end);
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return 0;
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}
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printk(KERN_INFO
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"IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
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dev_name(dev), start, end);
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pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
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dev_name(dev), start, end);
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if (end < start) {
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WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
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"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
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@ -2421,12 +2419,11 @@ static inline void iommu_prepare_isa(void)
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if (!pdev)
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return;
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printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
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pr_info("Prepare 0-16MiB unity mapping for LPC\n");
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ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
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if (ret)
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printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
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"floppy might not work\n");
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pr_err("Failed to create 0-16MiB identity map - floppy might not work\n");
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pci_dev_put(pdev);
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}
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@ -2470,7 +2467,7 @@ static int __init si_domain_init(int hw)
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return -EFAULT;
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}
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pr_debug("IOMMU: identity mapping domain is domain %d\n",
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pr_debug("Identity mapping domain is domain %d\n",
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si_domain->id);
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if (hw)
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@ -2670,8 +2667,8 @@ static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw
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hw ? CONTEXT_TT_PASS_THROUGH :
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CONTEXT_TT_MULTI_LEVEL);
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if (!ret)
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pr_info("IOMMU: %s identity mapping for device %s\n",
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hw ? "hardware" : "software", dev_name(dev));
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pr_info("%s identity mapping for device %s\n",
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hw ? "Hardware" : "Software", dev_name(dev));
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else if (ret == -ENODEV)
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/* device not associated with an iommu */
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ret = 0;
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@ -2748,12 +2745,12 @@ static void intel_iommu_init_qi(struct intel_iommu *iommu)
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*/
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iommu->flush.flush_context = __iommu_flush_context;
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iommu->flush.flush_iotlb = __iommu_flush_iotlb;
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pr_info("IOMMU: %s using Register based invalidation\n",
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pr_info("%s: Using Register based invalidation\n",
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iommu->name);
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} else {
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iommu->flush.flush_context = qi_flush_context;
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iommu->flush.flush_iotlb = qi_flush_iotlb;
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pr_info("IOMMU: %s using Queued invalidation\n", iommu->name);
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pr_info("%s: Using Queued invalidation\n", iommu->name);
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}
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}
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@ -2781,8 +2778,7 @@ static int __init init_dmars(void)
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g_num_of_iommus++;
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continue;
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}
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printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
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DMAR_UNITS_SUPPORTED);
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pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED);
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}
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/* Preallocate enough resources for IOMMU hot-addition */
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@ -2792,7 +2788,7 @@ static int __init init_dmars(void)
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g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
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GFP_KERNEL);
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if (!g_iommus) {
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printk(KERN_ERR "Allocating global iommu array failed\n");
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pr_err("Allocating global iommu array failed\n");
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ret = -ENOMEM;
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goto error;
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}
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@ -2843,7 +2839,7 @@ static int __init init_dmars(void)
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if (iommu_identity_mapping) {
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ret = iommu_prepare_static_identity_mapping(hw_pass_through);
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if (ret) {
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printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
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pr_crit("Failed to setup IOMMU pass-through\n");
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goto free_iommu;
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}
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}
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@ -2861,15 +2857,14 @@ static int __init init_dmars(void)
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* endfor
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* endfor
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*/
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printk(KERN_INFO "IOMMU: Setting RMRR:\n");
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pr_info("Setting RMRR:\n");
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for_each_rmrr_units(rmrr) {
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/* some BIOS lists non-exist devices in DMAR table. */
|
||||
for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
|
||||
i, dev) {
|
||||
ret = iommu_prepare_rmrr_dev(rmrr, dev);
|
||||
if (ret)
|
||||
printk(KERN_ERR
|
||||
"IOMMU: mapping reserved region failed\n");
|
||||
pr_err("Mapping reserved region failed\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -2944,7 +2939,7 @@ static struct iova *intel_alloc_iova(struct device *dev,
|
|||
}
|
||||
iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
|
||||
if (unlikely(!iova)) {
|
||||
printk(KERN_ERR "Allocating %ld-page iova for %s failed",
|
||||
pr_err("Allocating %ld-page iova for %s failed",
|
||||
nrpages, dev_name(dev));
|
||||
return NULL;
|
||||
}
|
||||
|
@ -2959,7 +2954,7 @@ static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
|
|||
|
||||
domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
|
||||
if (!domain) {
|
||||
printk(KERN_ERR "Allocating domain for %s failed",
|
||||
pr_err("Allocating domain for %s failed\n",
|
||||
dev_name(dev));
|
||||
return NULL;
|
||||
}
|
||||
|
@ -2968,7 +2963,7 @@ static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
|
|||
if (unlikely(!domain_context_mapped(dev))) {
|
||||
ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Domain context map for %s failed",
|
||||
pr_err("Domain context map for %s failed\n",
|
||||
dev_name(dev));
|
||||
return NULL;
|
||||
}
|
||||
|
@ -3010,8 +3005,8 @@ static int iommu_no_mapping(struct device *dev)
|
|||
* to non-identity mapping.
|
||||
*/
|
||||
domain_remove_one_dev_info(si_domain, dev);
|
||||
printk(KERN_INFO "32bit %s uses non-identity mapping\n",
|
||||
dev_name(dev));
|
||||
pr_info("32bit %s uses non-identity mapping\n",
|
||||
dev_name(dev));
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
|
@ -3026,8 +3021,8 @@ static int iommu_no_mapping(struct device *dev)
|
|||
CONTEXT_TT_PASS_THROUGH :
|
||||
CONTEXT_TT_MULTI_LEVEL);
|
||||
if (!ret) {
|
||||
printk(KERN_INFO "64bit %s uses identity mapping\n",
|
||||
dev_name(dev));
|
||||
pr_info("64bit %s uses identity mapping\n",
|
||||
dev_name(dev));
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
@ -3096,7 +3091,7 @@ static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
|
|||
error:
|
||||
if (iova)
|
||||
__free_iova(&domain->iovad, iova);
|
||||
printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
|
||||
pr_err("Device %s request: %zx@%llx dir %d --- failed\n",
|
||||
dev_name(dev), size, (unsigned long long)paddr, dir);
|
||||
return 0;
|
||||
}
|
||||
|
@ -3411,7 +3406,7 @@ static inline int iommu_domain_cache_init(void)
|
|||
|
||||
NULL);
|
||||
if (!iommu_domain_cache) {
|
||||
printk(KERN_ERR "Couldn't create iommu_domain cache\n");
|
||||
pr_err("Couldn't create iommu_domain cache\n");
|
||||
ret = -ENOMEM;
|
||||
}
|
||||
|
||||
|
@ -3428,7 +3423,7 @@ static inline int iommu_devinfo_cache_init(void)
|
|||
SLAB_HWCACHE_ALIGN,
|
||||
NULL);
|
||||
if (!iommu_devinfo_cache) {
|
||||
printk(KERN_ERR "Couldn't create devinfo cache\n");
|
||||
pr_err("Couldn't create devinfo cache\n");
|
||||
ret = -ENOMEM;
|
||||
}
|
||||
|
||||
|
@ -3805,19 +3800,19 @@ static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
|
|||
return 0;
|
||||
|
||||
if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
|
||||
pr_warn("IOMMU: %s doesn't support hardware pass through.\n",
|
||||
pr_warn("%s: Doesn't support hardware pass through.\n",
|
||||
iommu->name);
|
||||
return -ENXIO;
|
||||
}
|
||||
if (!ecap_sc_support(iommu->ecap) &&
|
||||
domain_update_iommu_snooping(iommu)) {
|
||||
pr_warn("IOMMU: %s doesn't support snooping.\n",
|
||||
pr_warn("%s: Doesn't support snooping.\n",
|
||||
iommu->name);
|
||||
return -ENXIO;
|
||||
}
|
||||
sp = domain_update_iommu_superpage(iommu) - 1;
|
||||
if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
|
||||
pr_warn("IOMMU: %s doesn't support large page.\n",
|
||||
pr_warn("%s: Doesn't support large page.\n",
|
||||
iommu->name);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
@ -4048,7 +4043,7 @@ static int intel_iommu_memory_notifier(struct notifier_block *nb,
|
|||
start = mhp->start_pfn << PAGE_SHIFT;
|
||||
end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
|
||||
if (iommu_domain_identity_map(si_domain, start, end)) {
|
||||
pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
|
||||
pr_warn("Failed to build identity map for [%llx-%llx]\n",
|
||||
start, end);
|
||||
return NOTIFY_BAD;
|
||||
}
|
||||
|
@ -4066,7 +4061,7 @@ static int intel_iommu_memory_notifier(struct notifier_block *nb,
|
|||
|
||||
iova = find_iova(&si_domain->iovad, start_vpfn);
|
||||
if (iova == NULL) {
|
||||
pr_debug("dmar: failed get IOVA for PFN %lx\n",
|
||||
pr_debug("Failed get IOVA for PFN %lx\n",
|
||||
start_vpfn);
|
||||
break;
|
||||
}
|
||||
|
@ -4074,7 +4069,7 @@ static int intel_iommu_memory_notifier(struct notifier_block *nb,
|
|||
iova = split_and_remove_iova(&si_domain->iovad, iova,
|
||||
start_vpfn, last_vpfn);
|
||||
if (iova == NULL) {
|
||||
pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
|
||||
pr_warn("Failed to split IOVA PFN [%lx-%lx]\n",
|
||||
start_vpfn, last_vpfn);
|
||||
return NOTIFY_BAD;
|
||||
}
|
||||
|
@ -4200,10 +4195,10 @@ int __init intel_iommu_init(void)
|
|||
goto out_free_dmar;
|
||||
|
||||
if (list_empty(&dmar_rmrr_units))
|
||||
printk(KERN_INFO "DMAR: No RMRR found\n");
|
||||
pr_info("No RMRR found\n");
|
||||
|
||||
if (list_empty(&dmar_atsr_units))
|
||||
printk(KERN_INFO "DMAR: No ATSR found\n");
|
||||
pr_info("No ATSR found\n");
|
||||
|
||||
if (dmar_init_reserved_ranges()) {
|
||||
if (force_on)
|
||||
|
@ -4217,12 +4212,11 @@ int __init intel_iommu_init(void)
|
|||
if (ret) {
|
||||
if (force_on)
|
||||
panic("tboot: Failed to initialize DMARs\n");
|
||||
printk(KERN_ERR "IOMMU: dmar init failed\n");
|
||||
pr_err("Initialization failed\n");
|
||||
goto out_free_reserved_range;
|
||||
}
|
||||
up_write(&dmar_global_lock);
|
||||
printk(KERN_INFO
|
||||
"PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
|
||||
pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
|
||||
|
||||
init_timer(&unmap_timer);
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
|
@ -4364,13 +4358,11 @@ static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
|
|||
|
||||
dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
|
||||
if (!dmar_domain) {
|
||||
printk(KERN_ERR
|
||||
"intel_iommu_domain_init: dmar_domain == NULL\n");
|
||||
pr_err("Can't allocate dmar_domain\n");
|
||||
return NULL;
|
||||
}
|
||||
if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
|
||||
printk(KERN_ERR
|
||||
"intel_iommu_domain_init() failed\n");
|
||||
pr_err("Domain initialization failed\n");
|
||||
domain_exit(dmar_domain);
|
||||
return NULL;
|
||||
}
|
||||
|
@ -4429,7 +4421,7 @@ static int intel_iommu_attach_device(struct iommu_domain *domain,
|
|||
addr_width = cap_mgaw(iommu->cap);
|
||||
|
||||
if (dmar_domain->max_addr > (1LL << addr_width)) {
|
||||
printk(KERN_ERR "%s: iommu width (%d) is not "
|
||||
pr_err("%s: iommu width (%d) is not "
|
||||
"sufficient for the mapped address (%llx)\n",
|
||||
__func__, addr_width, dmar_domain->max_addr);
|
||||
return -EFAULT;
|
||||
|
@ -4483,7 +4475,7 @@ static int intel_iommu_map(struct iommu_domain *domain,
|
|||
/* check if minimum agaw is sufficient for mapped address */
|
||||
end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
|
||||
if (end < max_addr) {
|
||||
printk(KERN_ERR "%s: iommu width (%d) is not "
|
||||
pr_err("%s: iommu width (%d) is not "
|
||||
"sufficient for the mapped address (%llx)\n",
|
||||
__func__, dmar_domain->gaw, max_addr);
|
||||
return -EFAULT;
|
||||
|
@ -4624,7 +4616,7 @@ static const struct iommu_ops intel_iommu_ops = {
|
|||
static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
|
||||
{
|
||||
/* G4x/GM45 integrated gfx dmar support is totally busted. */
|
||||
printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
|
||||
pr_info("Disabling IOMMU for graphics on this chipset\n");
|
||||
dmar_map_gfx = 0;
|
||||
}
|
||||
|
||||
|
@ -4642,7 +4634,7 @@ static void quirk_iommu_rwbf(struct pci_dev *dev)
|
|||
* Mobile 4 Series Chipset neglects to set RWBF capability,
|
||||
* but needs it. Same seems to hold for the desktop versions.
|
||||
*/
|
||||
printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
|
||||
pr_info("Forcing write-buffer flush capability\n");
|
||||
rwbf_quirk = 1;
|
||||
}
|
||||
|
||||
|
@ -4672,11 +4664,11 @@ static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
|
|||
return;
|
||||
|
||||
if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
|
||||
printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
|
||||
pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
|
||||
dmar_map_gfx = 0;
|
||||
} else if (dmar_map_gfx) {
|
||||
/* we have to ensure the gfx device is idle before we flush */
|
||||
printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
|
||||
pr_info("Disabling batched IOTLB flush on Ironlake\n");
|
||||
intel_iommu_strict = 1;
|
||||
}
|
||||
}
|
||||
|
@ -4738,7 +4730,7 @@ static void __init check_tylersburg_isoch(void)
|
|||
iommu_identity_mapping |= IDENTMAP_AZALIA;
|
||||
return;
|
||||
}
|
||||
|
||||
printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
|
||||
|
||||
pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
|
||||
vtisochctrl);
|
||||
}
|
||||
|
|
|
@ -1,3 +1,6 @@
|
|||
|
||||
#define pr_fmt(fmt) "DMAR-IR: " fmt
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dmar.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
@ -100,8 +103,7 @@ static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
|
|||
}
|
||||
|
||||
if (mask > ecap_max_handle_mask(iommu->ecap)) {
|
||||
printk(KERN_ERR
|
||||
"Requested mask %x exceeds the max invalidation handle"
|
||||
pr_err("Requested mask %x exceeds the max invalidation handle"
|
||||
" mask value %Lx\n", mask,
|
||||
ecap_max_handle_mask(iommu->ecap));
|
||||
return -1;
|
||||
|
@ -333,7 +335,7 @@ static int set_ioapic_sid(struct irte *irte, int apic)
|
|||
up_read(&dmar_global_lock);
|
||||
|
||||
if (sid == 0) {
|
||||
pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
|
||||
pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
@ -360,7 +362,7 @@ static int set_hpet_sid(struct irte *irte, u8 id)
|
|||
up_read(&dmar_global_lock);
|
||||
|
||||
if (sid == 0) {
|
||||
pr_warning("Failed to set source-id of HPET block (%d)\n", id);
|
||||
pr_warn("Failed to set source-id of HPET block (%d)\n", id);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
@ -580,7 +582,7 @@ static void __init intel_cleanup_irq_remapping(void)
|
|||
}
|
||||
|
||||
if (x2apic_supported())
|
||||
pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
|
||||
pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
|
||||
}
|
||||
|
||||
static int __init intel_prepare_irq_remapping(void)
|
||||
|
@ -589,8 +591,7 @@ static int __init intel_prepare_irq_remapping(void)
|
|||
struct intel_iommu *iommu;
|
||||
|
||||
if (irq_remap_broken) {
|
||||
printk(KERN_WARNING
|
||||
"This system BIOS has enabled interrupt remapping\n"
|
||||
pr_warn("This system BIOS has enabled interrupt remapping\n"
|
||||
"on a chipset that contains an erratum making that\n"
|
||||
"feature unstable. To maintain system stability\n"
|
||||
"interrupt remapping is being disabled. Please\n"
|
||||
|
@ -606,7 +607,7 @@ static int __init intel_prepare_irq_remapping(void)
|
|||
return -ENODEV;
|
||||
|
||||
if (parse_ioapics_under_ir() != 1) {
|
||||
printk(KERN_INFO "Not enabling interrupt remapping\n");
|
||||
pr_info("Not enabling interrupt remapping\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
|
@ -667,8 +668,8 @@ static int __init intel_enable_irq_remapping(void)
|
|||
*/
|
||||
for_each_iommu(iommu, drhd)
|
||||
if (eim && !ecap_eim_support(iommu->ecap)) {
|
||||
printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
|
||||
" ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
|
||||
pr_info("DRHD %Lx: EIM not supported by DRHD, "
|
||||
" ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
|
||||
eim = 0;
|
||||
}
|
||||
eim_mode = eim;
|
||||
|
@ -682,7 +683,7 @@ static int __init intel_enable_irq_remapping(void)
|
|||
int ret = dmar_enable_qi(iommu);
|
||||
|
||||
if (ret) {
|
||||
printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
|
||||
pr_err("DRHD %Lx: failed to enable queued, "
|
||||
" invalidation, ecap %Lx, ret %d\n",
|
||||
drhd->reg_base_addr, iommu->ecap, ret);
|
||||
goto error;
|
||||
|
@ -1145,14 +1146,12 @@ static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec)
|
|||
down_read(&dmar_global_lock);
|
||||
iommu = map_dev_to_ir(dev);
|
||||
if (!iommu) {
|
||||
printk(KERN_ERR
|
||||
"Unable to map PCI %s to iommu\n", pci_name(dev));
|
||||
pr_err("Unable to map PCI %s to iommu\n", pci_name(dev));
|
||||
index = -ENOENT;
|
||||
} else {
|
||||
index = alloc_irte(iommu, irq, nvec);
|
||||
if (index < 0) {
|
||||
printk(KERN_ERR
|
||||
"Unable to allocate %d IRTE for PCI %s\n",
|
||||
pr_err("Unable to allocate %d IRTE for PCI %s\n",
|
||||
nvec, pci_name(dev));
|
||||
index = -ENOSPC;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue