ARM: 6447/3: sa1100: Put nanoEngine support back in the kernel
Adds Bright Star Engineering's nanoEngine board support to the kernel. Also: - Adds the nanoEngine memory chip to arch/arm/mach-sa1100/cpu-sa1110.c (Micron MT48LC8M16A2TG-75). - Increase in the sdram_params->name[] field length to accomodate the name of the memory chip. - Clean up of header content and order of arch/arm/mach-sa1100/cpu-sa1110.c Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Marcelo Roberto Jimenez
Russell King
parent
7decaa557a
commit
9f15d2caca
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@ -118,6 +118,14 @@ config SA1100_LART
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(also known as the LART). See <http://www.lartmaker.nl/> for
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information on the LART.
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config SA1100_NANOENGINE
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bool "nanoEngine"
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select CPU_FREQ_SA1110
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help
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Say Y here if you are using the Bright Star Engineering nanoEngine.
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See <http://www.brightstareng.com/arm/nanoeng.htm> for information
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on the BSE nanoEngine.
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config SA1100_PLEB
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bool "PLEB"
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select CPU_FREQ_SA1100
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@ -37,6 +37,8 @@ obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o
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obj-$(CONFIG_SA1100_LART) += lart.o
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led-$(CONFIG_SA1100_LART) += leds-lart.o
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obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o
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obj-$(CONFIG_SA1100_PLEB) += pleb.o
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obj-$(CONFIG_SA1100_SHANNON) += shannon.o
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@ -16,28 +16,24 @@
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*
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* The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
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*/
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <mach/hardware.h>
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#include <asm/cputype.h>
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#include <asm/mach-types.h>
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#include <asm/system.h>
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#include <mach/hardware.h>
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#include "generic.h"
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#undef DEBUG
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static struct cpufreq_driver sa1110_driver;
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struct sdram_params {
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const char name[16];
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const char name[20];
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u_char rows; /* bits */
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u_char cas_latency; /* cycles */
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u_char tck; /* clock cycle time (ns) */
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@ -107,6 +103,15 @@ static struct sdram_params sdram_tbl[] __initdata = {
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.twr = 8,
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.refresh = 64000,
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.cas_latency = 3,
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}, { /* Micron MT48LC8M16A2TG-75 */
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.name = "MT48LC8M16A2TG-75",
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.rows = 12,
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.tck = 8,
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.trcd = 20,
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.trp = 20,
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.twr = 8,
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.refresh = 64000,
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.cas_latency = 3,
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},
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};
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@ -336,7 +341,9 @@ static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
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return 0;
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}
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static struct cpufreq_driver sa1110_driver = {
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/* sa1110_driver needs __refdata because it must remain after init registers
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* it with cpufreq_register_driver() */
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static struct cpufreq_driver sa1110_driver __refdata = {
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.flags = CPUFREQ_STICKY,
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.verify = sa11x0_verify_speed,
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.target = sa1110_target,
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@ -369,14 +376,14 @@ static int __init sa1110_clk_init(void)
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if (!name[0]) {
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if (machine_is_assabet())
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name = "TC59SM716-CL3";
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if (machine_is_pt_system3())
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name = "K4S641632D";
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if (machine_is_h3100())
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name = "KM416S4030CT";
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if (machine_is_jornada720())
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name = "K4S281632B-1H";
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if (machine_is_nanoengine())
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name = "MT48LC8M16A2TG-75";
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}
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sdram = sa1110_find_sdram(name);
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112
arch/arm/mach-sa1100/nanoengine.c
Normal file
112
arch/arm/mach-sa1100/nanoengine.c
Normal file
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@ -0,0 +1,112 @@
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/*
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* linux/arch/arm/mach-sa1100/nanoengine.c
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*
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* Bright Star Engineering's nanoEngine board init code.
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*
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* Copyright (C) 2009 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/root_dev.h>
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#include <asm/mach-types.h>
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#include <asm/setup.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/map.h>
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#include <asm/mach/serial_sa1100.h>
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#include <mach/hardware.h>
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#include "generic.h"
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/* Flash bank 0 */
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static struct mtd_partition nanoengine_partitions[] = {
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{
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.name = "nanoEngine boot firmware and parameter table",
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.size = 0x00010000, /* 32K */
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.offset = 0,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel/initrd reserved",
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.size = 0x002f0000,
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.offset = 0x00010000,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "experimental filesystem allocation",
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.size = 0x00100000,
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.offset = 0x00300000,
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.mask_flags = MTD_WRITEABLE,
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}
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};
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static struct flash_platform_data nanoengine_flash_data = {
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.map_name = "jedec_probe",
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.parts = nanoengine_partitions,
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.nr_parts = ARRAY_SIZE(nanoengine_partitions),
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};
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static struct resource nanoengine_flash_resources[] = {
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{
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.start = SA1100_CS0_PHYS,
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.end = SA1100_CS0_PHYS + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = SA1100_CS1_PHYS,
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.end = SA1100_CS1_PHYS + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct map_desc nanoengine_io_desc[] __initdata = {
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{
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/* System Registers */
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.virtual = 0xf0000000,
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.pfn = __phys_to_pfn(0x10000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}, {
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/* Internal PCI Config Space */
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.virtual = 0xf1000000,
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.pfn = __phys_to_pfn(0x18A00000),
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.length = 0x00100000,
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.type = MT_DEVICE
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}
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};
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static void __init nanoengine_map_io(void)
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{
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sa1100_map_io();
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iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
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sa1100_register_uart(0, 1);
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sa1100_register_uart(1, 2);
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sa1100_register_uart(2, 3);
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Ser1SDCR0 |= SDCR0_UART;
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/* disable IRDA -- UART2 is used as a normal serial port */
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Ser2UTCR4 = 0;
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Ser2HSCR0 = 0;
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}
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static void __init nanoengine_init(void)
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{
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sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
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ARRAY_SIZE(nanoengine_flash_resources));
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}
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MACHINE_START(NANOENGINE, "BSE nanoEngine")
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.boot_params = 0xc0000000,
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.map_io = nanoengine_map_io,
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.init_irq = sa1100_init_irq,
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.timer = &sa1100_timer,
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.init_machine = nanoengine_init,
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MACHINE_END
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