x86/bugs: Rename _RDS to _SSBD
Intel collateral will reference the SSB mitigation bit in IA32_SPEC_CTL[2] as SSBD (Speculative Store Bypass Disable). Hence changing it. It is unclear yet what the MSR_IA32_ARCH_CAPABILITIES (0x10a) Bit(4) name is going to be. Following the rename it would be SSBD_NO but that rolls out to Speculative Store Bypass Disable No. Also fixed the missing space in X86_FEATURE_AMD_SSBD. [ tglx: Fixup x86_amd_rds_enable() and rds_tif_to_amd_ls_cfg() as well ] Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
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@ -215,7 +215,7 @@
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#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
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#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
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#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
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#define X86_FEATURE_AMD_RDS (7*32+24) /* "" AMD RDS implementation */
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#define X86_FEATURE_AMD_SSBD ( 7*32+24) /* "" AMD SSBD implementation */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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@ -336,7 +336,7 @@
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#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
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#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
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#define X86_FEATURE_RDS (18*32+31) /* Reduced Data Speculation */
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#define X86_FEATURE_SSBD (18*32+31) /* Speculative Store Bypass Disable */
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/*
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* BUG word(s)
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@ -42,8 +42,8 @@
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#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
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#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */
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#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */
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#define SPEC_CTRL_RDS_SHIFT 2 /* Reduced Data Speculation bit */
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#define SPEC_CTRL_RDS (1 << SPEC_CTRL_RDS_SHIFT) /* Reduced Data Speculation */
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#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
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#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
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#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
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#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */
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@ -70,10 +70,10 @@
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#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
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#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
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#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */
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#define ARCH_CAP_RDS_NO (1 << 4) /*
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#define ARCH_CAP_SSBD_NO (1 << 4) /*
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* Not susceptible to Speculative Store Bypass
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* attack, so no Reduced Data Speculation control
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* required.
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* attack, so no Speculative Store Bypass
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* control required.
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*/
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#define MSR_IA32_BBL_CR_CTL 0x00000119
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@ -17,20 +17,20 @@ extern void x86_spec_ctrl_restore_host(u64);
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/* AMD specific Speculative Store Bypass MSR data */
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extern u64 x86_amd_ls_cfg_base;
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extern u64 x86_amd_ls_cfg_rds_mask;
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extern u64 x86_amd_ls_cfg_ssbd_mask;
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/* The Intel SPEC CTRL MSR base value cache */
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extern u64 x86_spec_ctrl_base;
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static inline u64 rds_tif_to_spec_ctrl(u64 tifn)
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static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
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{
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BUILD_BUG_ON(TIF_RDS < SPEC_CTRL_RDS_SHIFT);
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return (tifn & _TIF_RDS) >> (TIF_RDS - SPEC_CTRL_RDS_SHIFT);
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BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
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return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
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}
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static inline u64 rds_tif_to_amd_ls_cfg(u64 tifn)
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static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
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{
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return (tifn & _TIF_RDS) ? x86_amd_ls_cfg_rds_mask : 0ULL;
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return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
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}
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extern void speculative_store_bypass_update(void);
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@ -79,7 +79,7 @@ struct thread_info {
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#define TIF_SIGPENDING 2 /* signal pending */
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#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
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#define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/
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#define TIF_RDS 5 /* Reduced data speculation */
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#define TIF_SSBD 5 /* Reduced data speculation */
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#define TIF_SYSCALL_EMU 6 /* syscall emulation active */
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#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
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#define TIF_SECCOMP 8 /* secure computing */
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@ -106,7 +106,7 @@ struct thread_info {
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#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
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#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
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#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
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#define _TIF_RDS (1 << TIF_RDS)
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#define _TIF_SSBD (1 << TIF_SSBD)
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#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU)
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#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
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#define _TIF_SECCOMP (1 << TIF_SECCOMP)
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@ -146,7 +146,7 @@ struct thread_info {
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/* flags to check in __switch_to() */
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#define _TIF_WORK_CTXSW \
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(_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_RDS)
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(_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_SSBD)
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#define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)
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#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW)
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@ -567,12 +567,12 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
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}
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/*
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* Try to cache the base value so further operations can
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* avoid RMW. If that faults, do not enable RDS.
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* avoid RMW. If that faults, do not enable SSBD.
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*/
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if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
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setup_force_cpu_cap(X86_FEATURE_RDS);
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setup_force_cpu_cap(X86_FEATURE_AMD_RDS);
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x86_amd_ls_cfg_rds_mask = 1ULL << bit;
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setup_force_cpu_cap(X86_FEATURE_SSBD);
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setup_force_cpu_cap(X86_FEATURE_AMD_SSBD);
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x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
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}
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}
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}
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@ -920,9 +920,9 @@ static void init_amd(struct cpuinfo_x86 *c)
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if (!cpu_has(c, X86_FEATURE_XENPV))
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set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
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if (boot_cpu_has(X86_FEATURE_AMD_RDS)) {
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set_cpu_cap(c, X86_FEATURE_RDS);
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set_cpu_cap(c, X86_FEATURE_AMD_RDS);
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if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) {
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set_cpu_cap(c, X86_FEATURE_SSBD);
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set_cpu_cap(c, X86_FEATURE_AMD_SSBD);
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}
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}
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@ -45,10 +45,10 @@ static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
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/*
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* AMD specific MSR info for Speculative Store Bypass control.
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* x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
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* x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
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*/
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u64 __ro_after_init x86_amd_ls_cfg_base;
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u64 __ro_after_init x86_amd_ls_cfg_rds_mask;
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u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
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void __init check_bugs(void)
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{
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@ -146,7 +146,7 @@ u64 x86_spec_ctrl_get_default(void)
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u64 msrval = x86_spec_ctrl_base;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
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msrval |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
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msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
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return msrval;
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}
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
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@ -159,7 +159,7 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
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return;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
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host |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
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host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
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if (host != guest_spec_ctrl)
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wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl);
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return;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
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host |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
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host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
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if (host != guest_spec_ctrl)
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wrmsrl(MSR_IA32_SPEC_CTRL, host);
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}
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);
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static void x86_amd_rds_enable(void)
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static void x86_amd_ssb_disable(void)
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{
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u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_rds_mask;
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u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
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if (boot_cpu_has(X86_FEATURE_AMD_RDS))
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if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
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wrmsrl(MSR_AMD64_LS_CFG, msrval);
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}
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enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
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enum ssb_mitigation_cmd cmd;
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if (!boot_cpu_has(X86_FEATURE_RDS))
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if (!boot_cpu_has(X86_FEATURE_SSBD))
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return mode;
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cmd = ssb_parse_cmdline();
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/*
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* We have three CPU feature flags that are in play here:
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* - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
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* - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass
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* - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
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* - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
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*/
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if (mode == SPEC_STORE_BYPASS_DISABLE) {
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*/
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_INTEL:
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x86_spec_ctrl_base |= SPEC_CTRL_RDS;
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x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS;
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x86_spec_ctrl_set(SPEC_CTRL_RDS);
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x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
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x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
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x86_spec_ctrl_set(SPEC_CTRL_SSBD);
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break;
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case X86_VENDOR_AMD:
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x86_amd_rds_enable();
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x86_amd_ssb_disable();
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break;
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}
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}
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if (task_spec_ssb_force_disable(task))
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return -EPERM;
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task_clear_spec_ssb_disable(task);
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update = test_and_clear_tsk_thread_flag(task, TIF_RDS);
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update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
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break;
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case PR_SPEC_DISABLE:
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task_set_spec_ssb_disable(task);
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update = !test_and_set_tsk_thread_flag(task, TIF_RDS);
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update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
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break;
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case PR_SPEC_FORCE_DISABLE:
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task_set_spec_ssb_disable(task);
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task_set_spec_ssb_force_disable(task);
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update = !test_and_set_tsk_thread_flag(task, TIF_RDS);
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update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
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break;
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default:
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return -ERANGE;
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x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
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if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
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x86_amd_rds_enable();
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x86_amd_ssb_disable();
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}
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#ifdef CONFIG_SYSFS
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@ -959,7 +959,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
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rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
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if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
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!(ia32_cap & ARCH_CAP_RDS_NO))
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!(ia32_cap & ARCH_CAP_SSBD_NO))
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setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
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if (x86_match_cpu(cpu_no_speculation))
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@ -189,7 +189,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
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setup_clear_cpu_cap(X86_FEATURE_STIBP);
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setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
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setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
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setup_clear_cpu_cap(X86_FEATURE_RDS);
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setup_clear_cpu_cap(X86_FEATURE_SSBD);
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}
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/*
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@ -283,11 +283,11 @@ static __always_inline void __speculative_store_bypass_update(unsigned long tifn
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{
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u64 msr;
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if (static_cpu_has(X86_FEATURE_AMD_RDS)) {
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msr = x86_amd_ls_cfg_base | rds_tif_to_amd_ls_cfg(tifn);
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if (static_cpu_has(X86_FEATURE_AMD_SSBD)) {
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msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
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wrmsrl(MSR_AMD64_LS_CFG, msr);
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} else {
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msr = x86_spec_ctrl_base | rds_tif_to_spec_ctrl(tifn);
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msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
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wrmsrl(MSR_IA32_SPEC_CTRL, msr);
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}
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}
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if ((tifp ^ tifn) & _TIF_NOCPUID)
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set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
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if ((tifp ^ tifn) & _TIF_RDS)
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if ((tifp ^ tifn) & _TIF_SSBD)
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__speculative_store_bypass_update(tifn);
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}
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@ -407,7 +407,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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/* cpuid 7.0.edx*/
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const u32 kvm_cpuid_7_0_edx_x86_features =
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F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(RDS) |
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F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(SSBD) |
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F(ARCH_CAPABILITIES);
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/* all calls to cpuid_count() should be made on the same cpu */
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@ -3525,7 +3525,7 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_RDS))
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!guest_cpuid_has(vcpu, X86_FEATURE_SSBD))
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return 1;
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msr_info->data = to_vmx(vcpu)->spec_ctrl;
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_RDS))
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!guest_cpuid_has(vcpu, X86_FEATURE_SSBD))
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return 1;
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/* The STIBP bit doesn't fault even if it's not advertised */
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if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_RDS))
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if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
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return 1;
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vmx->spec_ctrl = data;
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