Pin control fixes for v5.2:
- Interrupt clearing fix for the Intel pin controllers affecting touchpads on some laptops. - Compile Kconfig fix for the STMFX expander pin controller. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJc7POsAAoJEEEQszewGV1zh1sP+gLYet9hCIOdinJFznOIT6P9 ncl6clClf+mhKpNX8DRhXGF1OWxx2Us2uXjtanUA/K7GmdazUDK3b80OX/xYFMnX RumR2VcABGk8vs6hh6qD92xm5PXc/IOelM1i4k29o9TpKXffaqME7BgTCsR9gjSL G4X3JH5kPxLjy41iKskO8ipyhtocUXhL43WrXh4tGilVKYFMtvJhwUpw2/UDj4Sw ex6ZjUwlj5sjYHpB52jb4NeHqPMOgPDu7St6YakoMtfu5aR0kaTOvqRwnQWjmY6m 6/Sna3/x8oly9k77uw/ruZrmGoseYeGjrEpAEdYt2bcNM0TsudULc24vnArVG/n3 ucv4RZ4Km2M1G/EOskSyTuxomjAcyIbIJ+ZdllGsAOcyraqd2kHvVIwReOdDyLta FQWDedA1KZRRnCC7GOIVtlDIoyMS3JnxXCAvVuFW2ybqoJy4HRgCot7ZaAtpeosm Bk7Yb4zd4wIyQvxHruaaT7MLfG1mRShkeV8c4NCot/ILO5m2uJ6L55x7ta+OU/vy sd29+ww8BN1UR6x06faQpvXv6KXKJmSWFGENGq1aW3WmkmOJnkit8gvAzhTbtW1S 17ezYJLwzD0tUzj/laAzqV3gXc9XwvA1nVciwWPzm+yEaa2VlsATam8+THPQF3aU UJODDGHn9EY5yM1Q5Eyt =XtxG -----END PGP SIGNATURE----- Merge tag 'pinctrl-v5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "The commits that stand out are the Intel fixes that arrived during the merge window and I got relayed by pull request from Andy. Apart from that a minor Kconfig noise. - Interrupt clearing fix for the Intel pin controllers affecting touchpads on some laptops. - Compile Kconfig fix for the STMFX expander pin controller" * tag 'pinctrl-v5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: stmfx: Fix compile issue when CONFIG_OF_GPIO is not defined pinctrl: intel: Clear interrupt status in mask/unmask callback pinctrl: intel: Use GENMASK() consistently
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commit
9fb67d643f
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@ -277,7 +277,7 @@ config PINCTRL_ST
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config PINCTRL_STMFX
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tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
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depends on I2C
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depends on OF || COMPILE_TEST
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depends on OF_GPIO
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select GENERIC_PINCONF
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select GPIOLIB_IRQCHIP
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select MFD_STMFX
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@ -33,13 +33,13 @@
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#define PADOWN_BITS 4
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#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
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#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
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#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
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#define PADOWN_GPP(p) ((p) / 8)
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/* Offset from pad_regs */
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#define PADCFG0 0x000
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#define PADCFG0_RXEVCFG_SHIFT 25
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#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
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#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
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#define PADCFG0_RXEVCFG_LEVEL 0
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#define PADCFG0_RXEVCFG_EDGE 1
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#define PADCFG0_RXEVCFG_DISABLED 2
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@ -51,7 +51,7 @@
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#define PADCFG0_GPIROUTSMI BIT(18)
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#define PADCFG0_GPIROUTNMI BIT(17)
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#define PADCFG0_PMODE_SHIFT 10
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#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
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#define PADCFG0_PMODE_MASK GENMASK(13, 10)
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#define PADCFG0_GPIORXDIS BIT(9)
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#define PADCFG0_GPIOTXDIS BIT(8)
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#define PADCFG0_GPIORXSTATE BIT(1)
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@ -60,7 +60,7 @@
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#define PADCFG1 0x004
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#define PADCFG1_TERM_UP BIT(13)
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#define PADCFG1_TERM_SHIFT 10
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#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
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#define PADCFG1_TERM_MASK GENMASK(12, 10)
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#define PADCFG1_TERM_20K 4
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#define PADCFG1_TERM_2K 3
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#define PADCFG1_TERM_5K 2
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@ -914,35 +914,6 @@ static void intel_gpio_irq_ack(struct irq_data *d)
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}
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}
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static void intel_gpio_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct intel_community *community;
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const struct intel_padgroup *padgrp;
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int pin;
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pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
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if (pin >= 0) {
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unsigned int gpp, gpp_offset, is_offset;
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unsigned long flags;
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u32 value;
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gpp = padgrp->reg_num;
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gpp_offset = padgroup_offset(padgrp, pin);
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is_offset = community->is_offset + gpp * 4;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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/* Clear interrupt status first to avoid unexpected interrupt */
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writel(BIT(gpp_offset), community->regs + is_offset);
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value = readl(community->regs + community->ie_offset + gpp * 4);
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value |= BIT(gpp_offset);
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writel(value, community->regs + community->ie_offset + gpp * 4);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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}
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static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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@ -955,15 +926,20 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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if (pin >= 0) {
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unsigned int gpp, gpp_offset;
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unsigned long flags;
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void __iomem *reg;
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void __iomem *reg, *is;
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u32 value;
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gpp = padgrp->reg_num;
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gpp_offset = padgroup_offset(padgrp, pin);
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reg = community->regs + community->ie_offset + gpp * 4;
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is = community->regs + community->is_offset + gpp * 4;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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/* Clear interrupt status first to avoid unexpected interrupt */
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writel(BIT(gpp_offset), is);
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value = readl(reg);
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if (mask)
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value &= ~BIT(gpp_offset);
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@ -1107,7 +1083,6 @@ static irqreturn_t intel_gpio_irq(int irq, void *data)
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static struct irq_chip intel_gpio_irqchip = {
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.name = "intel-gpio",
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.irq_enable = intel_gpio_irq_enable,
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.irq_ack = intel_gpio_irq_ack,
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.irq_mask = intel_gpio_irq_mask,
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.irq_unmask = intel_gpio_irq_unmask,
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