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MLK-18220-2 XRDC:Fix power domain and clock entries in DTS 

Ensure that every resource is associated with a power domain
and clocks required.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
pull/10/head
Ranjani Vaidyanathan 2018-05-07 16:40:16 -05:00 committed by Jason Liu
parent c1843f2a93
commit 9ff9793b58
2 changed files with 80 additions and 19 deletions
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94
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
View File

@ -321,13 +321,17 @@
reg = <SC_R_USB_0>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
#address-cells = <1>;
#size-cells = <0>;
wakeup-irq = <267>;
};
pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
reg = <SC_R_USB_0_PHY>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <267>;
pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
reg = <SC_R_USB_0_PHY>;
#power-domain-cells = <0>;
power-domains = <&pd_conn_usbotg0>;
wakeup-irq = <267>;
};
};
pd_conn_usbotg1: PD_CONN_USB_1 {
reg = <SC_R_USB_1>;
@ -337,14 +341,18 @@
pd_conn_usb2: PD_CONN_USB_2 {
reg = <SC_R_USB_2>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <271>;
};
pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
reg = <SC_R_USB_2_PHY>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <271>;
pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
reg = <SC_R_USB_2_PHY>;
#power-domain-cells = <0>;
power-domains = <&pd_conn_usb2>;
wakeup-irq = <271>;
};
};
pd_conn_sdch0: PD_CONN_SDHC_0 {
reg = <SC_R_SDHC_0>;
@ -719,17 +727,25 @@
#address-cells = <1>;
#size-cells = <0>;
pd_serdes1: PD_HSIO_SERDES_1 {
reg = <SC_R_SERDES_1>;
pd_hsio_gpio: PD_HSIO_GPIO {
reg = <SC_R_HSIO_GPIO>;
#power-domain-cells = <0>;
power-domains =<&pd_hsio>;
#address-cells = <1>;
#size-cells = <0>;
pd_pcie: PD_HSIO_PCIE_B {
reg = <SC_R_PCIE_B>;
pd_serdes1: PD_HSIO_SERDES_1 {
reg = <SC_R_SERDES_1>;
#power-domain-cells = <0>;
power-domains =<&pd_serdes1>;
power-domains =<&pd_hsio_gpio>;
#address-cells = <1>;
#size-cells = <0>;
pd_pcie: PD_HSIO_PCIE_B {
reg = <SC_R_PCIE_B>;
#power-domain-cells = <0>;
power-domains =<&pd_serdes1>;
};
};
};
};
@ -954,6 +970,29 @@
power-domains =<&pd_isi_ch0>;
};
};
pd_caam: PD_CAAM {
compatible = "nxp,imx8-pd";
reg = <SC_R_LAST>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_caam_jr1: PD_CAAM_JR1 {
reg = <SC_R_CAAM_JR1>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
pd_caam_jr2: PD_CAAM_JR2 {
reg = <SC_R_CAAM_JR2>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
pd_caam_jr3: PD_CAAM_JR3 {
reg = <SC_R_CAAM_JR3>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
};
};
tsens: thermal-sensor {
@ -1786,6 +1825,7 @@
<&clk IMX8QXP_IMG_JPEG_DEC_CLK >;
assigned-clock-rates = <200000000>;
power-domains =<&pd_jpgdec>;
status = "okay";
};
jpegenc: jpegenc@58450000 {
@ -1799,6 +1839,7 @@
<&clk IMX8QXP_IMG_JPEG_ENC_CLK >;
assigned-clock-rates = <200000000>;
power-domains =<&pd_jpgenc>;
status = "okay";
};
};
@ -1978,6 +2019,8 @@
power-domains = <&pd_lsio_gpio0>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QXP_LSIO_GPIO0_IPG_S_CLK>;
clock-names = "ipg";
};
gpio1: gpio@5d090000 {
@ -1989,6 +2032,8 @@
power-domains = <&pd_lsio_gpio1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QXP_LSIO_GPIO1_IPG_S_CLK>;
clock-names = "ipg";
};
gpio2: gpio@5d0a0000 {
@ -2000,6 +2045,8 @@
power-domains = <&pd_lsio_gpio2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QXP_LSIO_GPIO2_IPG_S_CLK>;
clock-names = "ipg";
};
gpio3: gpio@5d0b0000 {
@ -2011,6 +2058,8 @@
power-domains = <&pd_lsio_gpio3>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QXP_LSIO_GPIO3_IPG_S_CLK>;
clock-names = "ipg";
};
gpio4: gpio@5d0c0000 {
@ -2019,9 +2068,11 @@
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio4>;
power-domains = <&pd_lsio_gpio4>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QXP_LSIO_GPIO4_IPG_S_CLK>;
clock-names = "ipg";
};
gpio5: gpio@5d0d0000 {
@ -2033,6 +2084,8 @@
power-domains = <&pd_lsio_gpio5>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QXP_LSIO_GPIO5_IPG_S_CLK>;
clock-names = "ipg";
};
gpio6: gpio@5d0e0000 {
@ -2044,6 +2097,8 @@
power-domains = <&pd_lsio_gpio6>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QXP_LSIO_GPIO6_IPG_S_CLK>;
clock-names = "ipg";
};
gpio7: gpio@5d0f0000 {
@ -2055,6 +2110,8 @@
power-domains = <&pd_lsio_gpio7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX8QXP_LSIO_GPIO7_IPG_S_CLK>;
clock-names = "ipg";
};
gpio0_mipi_csi0: gpio@58222000 {
@ -2739,7 +2796,6 @@
clocks = <&clk IMX8QXP_CM40_IPG_CLK>;
clock-names = "ipg";
power-domains = <&pd_cm40_mu0a0>;
status = "okay";
};
rpmsg: rpmsg{

5
include/dt-bindings/soc/imx8_pd.h
View File

@ -206,5 +206,10 @@
#define PD_CM41_I2C cm41_i2c
#define PD_CM41_INTMUX cm41_intmux
#define PD_CAAM caam_power_domain
#define PD_CAAM_JR1 caam_job_ring1
#define PD_CAAM_JR2 caam_job_ring2
#define PD_CAAM_JR3 caam_job_ring3
#endif /* __DT_BINDINGS_IMX8_PD_H */