Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar: "Three fixes: - A boot crash fix with certain configs - a MAINTAINERS entry update - Documentation typo fixes" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/Documentation: Fix various typos in Documentation/x86/ files x86/amd_nb: Fix boot crash on non-AMD systems MAINTAINERS: Update the Calgary IOMMU entry
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a017f583ec
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@ -45,7 +45,7 @@ is how we expect the compiler, application and kernel to work together.
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MPX-instrumented.
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3) The kernel detects that the CPU has MPX, allows the new prctl() to
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succeed, and notes the location of the bounds directory. Userspace is
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expected to keep the bounds directory at that locationWe note it
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expected to keep the bounds directory at that location. We note it
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instead of reading it each time because the 'xsave' operation needed
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to access the bounds directory register is an expensive operation.
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4) If the application needs to spill bounds out of the 4 registers, it
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@ -167,7 +167,7 @@ If a #BR is generated due to a bounds violation caused by MPX.
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We need to decode MPX instructions to get violation address and
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set this address into extended struct siginfo.
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The _sigfault feild of struct siginfo is extended as follow:
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The _sigfault field of struct siginfo is extended as follow:
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87 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
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88 struct {
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@ -240,5 +240,5 @@ them at the same bounds table.
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This is allowed architecturally. See more information "Intel(R) Architecture
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Instruction Set Extensions Programming Reference" (9.3.4).
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However, if users did this, the kernel might be fooled in to unmaping an
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However, if users did this, the kernel might be fooled in to unmapping an
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in-use bounds table since it does not recognize sharing.
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@ -5,7 +5,7 @@ memory, it has two choices:
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from areas other than the one we are trying to flush will be
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destroyed and must be refilled later, at some cost.
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2. Use the invlpg instruction to invalidate a single page at a
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time. This could potentialy cost many more instructions, but
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time. This could potentially cost many more instructions, but
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it is a much more precise operation, causing no collateral
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damage to other TLB entries.
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@ -19,7 +19,7 @@ Which method to do depends on a few things:
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work.
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3. The size of the TLB. The larger the TLB, the more collateral
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damage we do with a full flush. So, the larger the TLB, the
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more attrative an individual flush looks. Data and
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more attractive an individual flush looks. Data and
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instructions have separate TLBs, as do different page sizes.
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4. The microarchitecture. The TLB has become a multi-level
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cache on modern CPUs, and the global flushes have become more
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@ -36,7 +36,7 @@ between all CPUs.
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check_interval
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How often to poll for corrected machine check errors, in seconds
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(Note output is hexademical). Default 5 minutes. When the poller
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(Note output is hexadecimal). Default 5 minutes. When the poller
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finds MCEs it triggers an exponential speedup (poll more often) on
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the polling interval. When the poller stops finding MCEs, it
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triggers an exponential backoff (poll less often) on the polling
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@ -71,8 +71,8 @@ int amd_cache_northbridges(void)
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while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
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i++;
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if (i == 0)
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return 0;
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if (!i)
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return -ENODEV;
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nb = kzalloc(i * sizeof(struct amd_northbridge), GFP_KERNEL);
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if (!nb)
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