mmc: sdhci-xenon: Fix default value of LOGIC_TIMING_ADJUST for eMMC5.0 PHY
The default value of LOGIC_TIMING_ADJUST register in eMMC 5.0 PHY is different from that in eMMC 5.1 PHY. Set the specific value for that register in eMMC 5.0 PHY. Signed-off-by: Hu Ziji <huziji@marvell.com> Reported-by: Jisheng Zhang <jszhang@marvell.com> Tested-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -108,6 +108,7 @@
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#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \
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(XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
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#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54
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#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
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#define XENON_LOGIC_TIMING_VALUE 0x00AA8977
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@ -130,6 +131,8 @@ struct xenon_emmc_phy_regs {
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u16 logic_timing_adj;
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/* DLL Update Enable bit */
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u32 dll_update;
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/* value in Logic Timing Adjustment register */
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u32 logic_timing_val;
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};
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static const char * const phy_types[] = {
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@ -166,6 +169,7 @@ static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
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.dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL,
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.logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
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.dll_update = XENON_DLL_UPDATE_STROBE_5_0,
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.logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE,
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};
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static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
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@ -176,6 +180,7 @@ static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
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.dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL,
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.logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
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.dll_update = XENON_DLL_UPDATE,
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.logic_timing_val = XENON_LOGIC_TIMING_VALUE,
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};
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/*
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@ -607,7 +612,7 @@ static void xenon_emmc_phy_set(struct sdhci_host *host,
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if (timing == MMC_TIMING_MMC_HS400)
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/* Hardware team recommend a value for HS400 */
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sdhci_writel(host, XENON_LOGIC_TIMING_VALUE,
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sdhci_writel(host, phy_regs->logic_timing_val,
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phy_regs->logic_timing_adj);
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else
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xenon_emmc_phy_disable_data_strobe(host);
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