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MLK-16571-3: arm64: dts: add i.MX8QM lpspi device node 

add the lpspi device node and change the peripheral to nor chip.
i.MX8QM also need both ipg and per clock for this module.

BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0

Reviewed-by: Pan Gao <pandy.gao@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
pull/10/head
Han Xu 2017-10-11 15:53:38 -05:00 committed by Jason Liu
parent fcd1132ed4
commit a06bef6d25
2 changed files with 19 additions and 9 deletions
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21
arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
View File

@ -409,11 +409,16 @@
SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c
SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c
SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c
SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c
SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c
>;
};
pinctrl_lpspi0_cs: lpspi0cs {
fsl,pins = <
SC_P_SPI0_CS0_LSIO_GPIO3_IO05 0x21
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
@ -719,15 +724,19 @@
&lpspi0 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi0>;
pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
cs-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
flash: at45db041e@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <500000>;
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <4000000>;
};
};
};
&lpuart0 { /* console */

7
arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
View File

@ -1865,10 +1865,11 @@
reg = <0x0 0x5a000000 0x0 0x10000>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_SPI0_CLK>;
clock-names = "ipg";
clocks = <&clk IMX8QM_SPI0_CLK>,
<&clk IMX8QM_SPI0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_SPI0_CLK>;
assigned-clock-rates = <32000000>;
assigned-clock-rates = <20000000>;
power-domains = <&pd_dma_lpspi0>;
status = "disabled";
};