drm/i915/gen9: Fix PCODE polling during CDCLK change notification
commit848496e590
Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Jul 13 16:32:03 2016 +0300 drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL increased the timeout to match the spec, but we still see a timeout on at least one SKL. A CDCLK change request following the failed one will succeed nevertheless. I could reproduce this problem easily by running kms_pipe_crc_basic in a loop. In all failure cases _wait_for() was pre-empted for >3ms and so in the worst case - when the pre-emption happened right after calculating timeout__ in _wait_for() - we called skl_cdclk_wait_for_pcu_ready() only once which failed and so _wait_for() timed out. As opposed to this the spec says to keep retrying the request for at most a 3ms period. To fix this send the first request explicitly to guarantee that there is 3ms between the first and last request. Though this matches the spec, I noticed that in rare cases this can still time out if we sent only a few requests (in the worst case 2) _and_ PCODE is busy for some reason even after a previous request and a 3ms delay. To work around this retry the polling with pre-emption disabled to maximize the number of requests. Also increase the timeout to 10ms to account for interrupts that could reduce the number of requests. With this change I couldn't trigger the problem. v2: - Use 1ms poll period instead of 10us. (Chris) v3: - Poll with pre-emption disabled to increase the number of request attempts. (Ville, Chris) - Factor out a helper to poll, it's also needed by the next patch. v4: - Pass reply_mask, reply to skl_pcode_request(), instead of assuming the reply is generic. (Ville) v5: - List the request specific timeout values as code comment. (Ville) v6: - Try the poll first with preemption enabled. - Add code comment about first request being queued by PCODE. (Art) - Add timeout_base_ms argument. (Ville) v7: - Clarify code comment about first queued request. (Chris) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Art Runyan <arthur.j.runyan@intel.com> Cc: <stable@vger.kernel.org> # v4.2- :3b2c171
: drm/i915: Wait up to 3ms Cc: <stable@vger.kernel.org> # v4.2- Fixes:5d96d8afcf
("drm/i915/skl: Deinit/init the display at suspend/resume") Reference: https://bugs.freedesktop.org/show_bug.cgi?id=97929 Testcase: igt/kms_pipe_crc_basic/suspend-read-crc-pipe-B Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1480955258-26311-1-git-send-email-imre.deak@intel.com
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@ -3705,6 +3705,8 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
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int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
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int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
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int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
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u32 reply_mask, u32 reply, int timeout_base_ms);
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/* intel_sideband.c */
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u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
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@ -6271,35 +6271,24 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
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dev_priv->cdclk_pll.vco = 0;
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}
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static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
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{
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int ret;
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u32 val;
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/* inform PCU we want to change CDCLK */
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val = SKL_CDCLK_PREPARE_FOR_CHANGE;
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mutex_lock(&dev_priv->rps.hw_lock);
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ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
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mutex_unlock(&dev_priv->rps.hw_lock);
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return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
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}
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static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
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{
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return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
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}
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static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
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{
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u32 freq_select, pcu_ack;
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int ret;
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WARN_ON((cdclk == 24000) != (vco == 0));
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DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
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if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
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DRM_ERROR("failed to inform PCU about cdclk change\n");
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mutex_lock(&dev_priv->rps.hw_lock);
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ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
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SKL_CDCLK_PREPARE_FOR_CHANGE,
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SKL_CDCLK_READY_FOR_CHANGE,
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SKL_CDCLK_READY_FOR_CHANGE, 3);
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mutex_unlock(&dev_priv->rps.hw_lock);
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if (ret) {
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DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
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ret);
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return;
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}
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@ -7896,6 +7896,81 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
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return 0;
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}
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static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
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u32 request, u32 reply_mask, u32 reply,
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u32 *status)
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{
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u32 val = request;
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*status = sandybridge_pcode_read(dev_priv, mbox, &val);
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return *status || ((val & reply_mask) == reply);
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}
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/**
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* skl_pcode_request - send PCODE request until acknowledgment
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* @dev_priv: device private
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* @mbox: PCODE mailbox ID the request is targeted for
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* @request: request ID
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* @reply_mask: mask used to check for request acknowledgment
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* @reply: value used to check for request acknowledgment
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* @timeout_base_ms: timeout for polling with preemption enabled
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*
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* Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
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* reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
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* The request is acknowledged once the PCODE reply dword equals @reply after
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* applying @reply_mask. Polling is first attempted with preemption enabled
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* for @timeout_base_ms and if this times out for another 10 ms with
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* preemption disabled.
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*
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* Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
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* other error as reported by PCODE.
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*/
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int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
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u32 reply_mask, u32 reply, int timeout_base_ms)
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{
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u32 status;
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int ret;
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WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
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#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
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&status)
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/*
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* Prime the PCODE by doing a request first. Normally it guarantees
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* that a subsequent request, at most @timeout_base_ms later, succeeds.
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* _wait_for() doesn't guarantee when its passed condition is evaluated
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* first, so send the first request explicitly.
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*/
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if (COND) {
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ret = 0;
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goto out;
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}
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ret = _wait_for(COND, timeout_base_ms * 1000, 10);
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if (!ret)
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goto out;
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/*
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* The above can time out if the number of requests was low (2 in the
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* worst case) _and_ PCODE was busy for some reason even after a
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* (queued) request and @timeout_base_ms delay. As a workaround retry
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* the poll with preemption disabled to maximize the number of
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* requests. Increase the timeout from @timeout_base_ms to 10ms to
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* account for interrupts that could reduce the number of these
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* requests.
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*/
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DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
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WARN_ON_ONCE(timeout_base_ms > 3);
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preempt_disable();
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ret = wait_for_atomic(COND, 10);
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preempt_enable();
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out:
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return ret ? ret : status;
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#undef COND
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}
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static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
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{
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/*
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