clk: samsung: exynos7: Correct CMU_FSYS0 clocks names
This patch renames CMU_FSYS0 clocks names to match with user manual. And also adds missing gate clock for aclk_fsys0_200. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -512,6 +512,9 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
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ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
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ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
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ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
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@ -849,13 +852,13 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
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/*
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* List of parent clocks for Muxes in CMU_FSYS0
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*/
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PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
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PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
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PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" };
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PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" };
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PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" };
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PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll",
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PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" };
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PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll",
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"phyclk_usbdrd300_udrd30_phyclock" };
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PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll",
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PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
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"phyclk_usbdrd300_udrd30_pipe_pclk" };
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/* fixed rate clocks used in the FSYS0 block */
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@ -878,18 +881,19 @@ static unsigned long fsys0_clk_regs[] __initdata = {
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};
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static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
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MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
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MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
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MUX_SEL_FSYS00, 24, 1),
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MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
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MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
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MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
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MUX_SEL_FSYS01, 24, 1),
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MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
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MUX_SEL_FSYS01, 28, 1),
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MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
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mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
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mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
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MUX_SEL_FSYS02, 24, 1),
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MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
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mout_phyclk_usbdrd300_udrd30_phyclk_p,
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mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
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MUX_SEL_FSYS02, 28, 1),
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};
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@ -62,7 +62,8 @@
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#define CLK_SCLK_MMC2 6
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#define CLK_SCLK_MMC1 7
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#define CLK_SCLK_MMC0 8
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#define TOP1_NR_CLK 9
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#define CLK_ACLK_FSYS0_200 9
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#define TOP1_NR_CLK 10
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/* CCORE */
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#define PCLK_RTC 1
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