clocksource: m86k: Convert to clocksource_register_hz/khz
Updated to merge the valid bits of the two m68k patches. This converts the m86k clocksources to use clocksource_register_hz/khz This is untested, so any assistance in testing would be appreciated! CC: Geert Uytterhoeven <geert@linux-m68k.org> CC: Greg Ungerer <gerg@uclinux.org> Signed-off-by: John Stultz <johnstul@us.ibm.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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@ -93,7 +93,6 @@ static struct clocksource m68328_clk = {
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.name = "timer",
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.rating = 250,
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.read = m68328_read_clk,
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.shift = 20,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -115,8 +114,7 @@ void hw_timer_init(void)
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/* Enable timer 1 */
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TCTL |= TCTL_TEN;
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m68328_clk.mult = clocksource_hz2mult(TICKS_PER_JIFFY*HZ, m68328_clk.shift);
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clocksource_register(&m68328_clk);
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clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ);
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}
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/***************************************************************************/
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@ -44,7 +44,6 @@ static struct clocksource clocksource_cf_dt = {
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.rating = 200,
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.read = cf_dt_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -60,9 +59,7 @@ static int __init init_cf_dt_clocksource(void)
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__raw_writeb(0x00, DTER0);
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__raw_writel(0x00000000, DTRR0);
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__raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
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clocksource_cf_dt.mult = clocksource_hz2mult(DMA_FREQ,
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clocksource_cf_dt.shift);
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return clocksource_register(&clocksource_cf_dt);
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return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
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}
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arch_initcall(init_cf_dt_clocksource);
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@ -144,7 +144,6 @@ static struct clocksource pit_clk = {
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.name = "pit",
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.rating = 100,
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.read = pit_read_clk,
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.shift = 20,
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.mask = CLOCKSOURCE_MASK(32),
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};
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@ -162,8 +161,7 @@ void hw_timer_init(void)
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setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
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pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
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clocksource_register(&pit_clk);
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clocksource_register_hz(&pit_clk, FREQ);
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}
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/***************************************************************************/
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@ -114,7 +114,6 @@ static struct clocksource mcfslt_clk = {
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.name = "slt",
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.rating = 250,
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.read = mcfslt_read_clk,
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.shift = 20,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -136,8 +135,7 @@ void hw_timer_init(void)
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setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
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mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
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clocksource_register(&mcfslt_clk);
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clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
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#ifdef CONFIG_HIGHPROFILE
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mcfslt_profile_init();
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@ -88,7 +88,6 @@ static struct clocksource mcftmr_clk = {
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.name = "tmr",
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.rating = 250,
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.read = mcftmr_read_clk,
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.shift = 20,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@ -109,8 +108,7 @@ void hw_timer_init(void)
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__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
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mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
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clocksource_register(&mcftmr_clk);
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clocksource_register_hz(&mcftmr_clk, FREQ);
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setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
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