drm/nv50-/disp: initial work towards supporting external encoders
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
5a885f0b75
commit
a2bc283f39
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@ -165,6 +165,7 @@ nouveau-y += core/engine/disp/hdanvd0.o
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nouveau-y += core/engine/disp/hdminv84.o
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nouveau-y += core/engine/disp/hdminva3.o
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nouveau-y += core/engine/disp/hdminvd0.o
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nouveau-y += core/engine/disp/piornv50.o
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nouveau-y += core/engine/disp/sornv50.o
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nouveau-y += core/engine/disp/sornv94.o
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nouveau-y += core/engine/disp/sornvd0.o
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@ -70,6 +70,7 @@ struct nouveau_dp_func {
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extern const struct nouveau_dp_func nv94_sor_dp_func;
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extern const struct nouveau_dp_func nvd0_sor_dp_func;
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extern const struct nouveau_dp_func nv50_pior_dp_func;
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int nouveau_dp_train(struct nouveau_disp *, const struct nouveau_dp_func *,
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struct dcb_output *, int, u32);
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@ -678,6 +678,9 @@ nv50_disp_base_omthds[] = {
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{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
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{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
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{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
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{},
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};
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@ -1227,9 +1230,12 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->head.nr = 2;
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priv->dac.nr = 3;
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priv->sor.nr = 2;
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priv->pior.nr = 3;
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priv->dac.power = nv50_dac_power;
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priv->dac.sense = nv50_dac_sense;
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priv->sor.power = nv50_sor_power;
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priv->pior.power = nv50_pior_power;
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priv->pior.dp = &nv50_pior_dp_func;
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return 0;
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}
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@ -35,6 +35,12 @@ struct nv50_disp_priv {
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u32 lvdsconf;
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const struct nouveau_dp_func *dp;
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} sor;
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struct {
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int nr;
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int (*power)(struct nv50_disp_priv *, int ext, u32 data);
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u8 type[3];
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const struct nouveau_dp_func *dp;
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} pior;
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};
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#define DAC_MTHD(n) (n), (n) + 0x03
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@ -73,6 +79,11 @@ int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
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int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
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struct dcb_output *);
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#define PIOR_MTHD(n) (n), (n) + 0x03
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int nv50_pior_mthd(struct nouveau_object *, u32, void *, u32);
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int nv50_pior_power(struct nv50_disp_priv *, int, u32);
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struct nv50_disp_base {
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struct nouveau_parent base;
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struct nouveau_ramht *ramht;
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@ -46,6 +46,9 @@ nv84_disp_base_omthds[] = {
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{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
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{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
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{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
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{},
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};
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@ -77,10 +80,13 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->head.nr = 2;
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priv->dac.nr = 3;
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priv->sor.nr = 2;
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priv->pior.nr = 3;
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priv->dac.power = nv50_dac_power;
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priv->dac.sense = nv50_dac_sense;
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priv->sor.power = nv50_sor_power;
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priv->sor.hdmi = nv84_hdmi_ctrl;
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priv->pior.power = nv50_pior_power;
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priv->pior.dp = &nv50_pior_dp_func;
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return 0;
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}
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@ -46,6 +46,9 @@ nv94_disp_base_omthds[] = {
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{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
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{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
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{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
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{},
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};
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@ -77,11 +80,14 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->head.nr = 2;
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priv->dac.nr = 3;
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priv->sor.nr = 4;
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priv->pior.nr = 3;
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priv->dac.power = nv50_dac_power;
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priv->dac.sense = nv50_dac_sense;
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priv->sor.power = nv50_sor_power;
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priv->sor.hdmi = nv84_hdmi_ctrl;
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priv->sor.dp = &nv94_sor_dp_func;
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priv->pior.power = nv50_pior_power;
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priv->pior.dp = &nv50_pior_dp_func;
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return 0;
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}
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@ -67,10 +67,13 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->head.nr = 2;
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priv->dac.nr = 3;
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priv->sor.nr = 2;
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priv->pior.nr = 3;
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priv->dac.power = nv50_dac_power;
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priv->dac.sense = nv50_dac_sense;
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priv->sor.power = nv50_sor_power;
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priv->sor.hdmi = nv84_hdmi_ctrl;
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priv->pior.power = nv50_pior_power;
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priv->pior.dp = &nv50_pior_dp_func;
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return 0;
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}
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@ -47,6 +47,9 @@ nva3_disp_base_omthds[] = {
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{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
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{ DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd },
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{ DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
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{ PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
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{},
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};
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@ -78,12 +81,15 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->head.nr = 2;
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priv->dac.nr = 3;
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priv->sor.nr = 4;
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priv->pior.nr = 3;
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priv->dac.power = nv50_dac_power;
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priv->dac.sense = nv50_dac_sense;
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priv->sor.power = nv50_sor_power;
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priv->sor.hda_eld = nva3_hda_eld;
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priv->sor.hdmi = nva3_hdmi_ctrl;
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priv->sor.dp = &nv94_sor_dp_func;
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priv->pior.power = nv50_pior_power;
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priv->pior.dp = &nv50_pior_dp_func;
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return 0;
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}
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140
drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c
Normal file
140
drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c
Normal file
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@ -0,0 +1,140 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <core/os.h>
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#include <core/class.h>
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#include <subdev/bios.h>
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#include <subdev/bios/dcb.h>
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#include <subdev/timer.h>
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#include <subdev/i2c.h>
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#include "nv50.h"
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/******************************************************************************
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* DisplayPort
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*****************************************************************************/
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static struct nouveau_i2c_port *
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nv50_pior_dp_find(struct nouveau_disp *disp, struct dcb_output *outp)
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{
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struct nouveau_i2c *i2c = nouveau_i2c(disp);
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return i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(outp->extdev));
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}
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static int
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nv50_pior_dp_pattern(struct nouveau_disp *disp, struct dcb_output *outp,
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int head, int pattern)
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{
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struct nouveau_i2c_port *port;
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int ret = -EINVAL;
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port = nv50_pior_dp_find(disp, outp);
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if (port) {
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if (port->func->pattern)
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ret = port->func->pattern(port, pattern);
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else
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ret = 0;
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}
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return ret;
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}
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static int
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nv50_pior_dp_lnk_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
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int head, int lane_nr, int link_bw, bool enh)
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{
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struct nouveau_i2c_port *port;
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int ret = -EINVAL;
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port = nv50_pior_dp_find(disp, outp);
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if (port && port->func->lnk_ctl)
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ret = port->func->lnk_ctl(port, lane_nr, link_bw, enh);
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return ret;
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}
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static int
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nv50_pior_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
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int head, int lane, int vsw, int pre)
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{
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struct nouveau_i2c_port *port;
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int ret = -EINVAL;
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port = nv50_pior_dp_find(disp, outp);
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if (port) {
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if (port->func->drv_ctl)
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ret = port->func->drv_ctl(port, lane, vsw, pre);
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else
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ret = 0;
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}
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return ret;
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}
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const struct nouveau_dp_func
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nv50_pior_dp_func = {
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.pattern = nv50_pior_dp_pattern,
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.lnk_ctl = nv50_pior_dp_lnk_ctl,
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.drv_ctl = nv50_pior_dp_drv_ctl,
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};
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/******************************************************************************
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* General PIOR handling
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*****************************************************************************/
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int
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nv50_pior_power(struct nv50_disp_priv *priv, int or, u32 data)
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{
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const u32 stat = data & NV50_DISP_PIOR_PWR_STATE;
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const u32 soff = (or * 0x800);
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nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000);
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nv_mask(priv, 0x61e004 + soff, 0x80000101, 0x80000000 | stat);
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nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000);
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return 0;
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}
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int
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nv50_pior_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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const u8 type = (mthd & NV50_DISP_PIOR_MTHD_TYPE) >> 12;
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const u8 or = (mthd & NV50_DISP_PIOR_MTHD_OR);
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u32 *data = args;
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int ret;
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if (size < sizeof(u32))
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return -EINVAL;
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mthd &= ~NV50_DISP_PIOR_MTHD_TYPE;
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mthd &= ~NV50_DISP_PIOR_MTHD_OR;
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switch (mthd) {
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case NV50_DISP_PIOR_PWR:
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ret = priv->pior.power(priv, or, data[0]);
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priv->pior.type[or] = type;
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break;
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default:
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return -EINVAL;
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}
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return ret;
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}
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@ -219,6 +219,23 @@ struct nv04_display_class {
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#define NV50_DISP_DAC_LOAD 0x0002000c
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#define NV50_DISP_DAC_LOAD_VALUE 0x00000007
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#define NV50_DISP_PIOR_MTHD 0x00030000
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#define NV50_DISP_PIOR_MTHD_TYPE 0x0000f000
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#define NV50_DISP_PIOR_MTHD_OR 0x00000003
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#define NV50_DISP_PIOR_PWR 0x00030000
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#define NV50_DISP_PIOR_PWR_STATE 0x00000001
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#define NV50_DISP_PIOR_PWR_STATE_ON 0x00000001
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#define NV50_DISP_PIOR_PWR_STATE_OFF 0x00000000
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#define NV50_DISP_PIOR_TMDS_PWR 0x00032000
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#define NV50_DISP_PIOR_TMDS_PWR_STATE 0x00000001
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#define NV50_DISP_PIOR_TMDS_PWR_STATE_ON 0x00000001
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#define NV50_DISP_PIOR_TMDS_PWR_STATE_OFF 0x00000000
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#define NV50_DISP_PIOR_DP_PWR 0x00036000
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#define NV50_DISP_PIOR_DP_PWR_STATE 0x00000001
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#define NV50_DISP_PIOR_DP_PWR_STATE_ON 0x00000001
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#define NV50_DISP_PIOR_DP_PWR_STATE_OFF 0x00000000
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struct nv50_display_class {
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};
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