[PATCH] ppc64: Fix runlatch code to work on pseries machines
Not all ppc64 CPUs have the CTRL SPR, so we need a cputable feature for it. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -81,7 +81,7 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "RS64-II (northstar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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@ -94,7 +94,7 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "RS64-III (pulsar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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@ -107,7 +107,7 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "RS64-III (icestar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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@ -120,7 +120,7 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "RS64-IV (sstar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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@ -138,6 +138,7 @@ extern firmware_feature_t firmware_features_table[];
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#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
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#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
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#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
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#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
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/* Platform firmware features */
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#define FW_FTR_ ASM_CONST(0x0000000000000001)
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@ -148,7 +149,7 @@ extern firmware_feature_t firmware_features_table[];
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#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
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CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
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CPU_FTR_NODSISRALIGN)
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CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
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/* iSeries doesn't support large pages */
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#ifdef CONFIG_PPC_ISERIES
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@ -20,6 +20,7 @@
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#include <asm/ptrace.h>
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#include <asm/types.h>
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#include <asm/systemcfg.h>
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#include <asm/cputable.h>
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/* Machine State Register (MSR) Fields */
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#define MSR_SF_LG 63 /* Enable 64 bit mode */
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@ -501,18 +502,22 @@ static inline void ppc64_runlatch_on(void)
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{
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unsigned long ctrl;
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ctrl = mfspr(SPRN_CTRLF);
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ctrl |= CTRL_RUNLATCH;
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mtspr(SPRN_CTRLT, ctrl);
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if (cpu_has_feature(CPU_FTR_CTRL)) {
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ctrl = mfspr(SPRN_CTRLF);
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ctrl |= CTRL_RUNLATCH;
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mtspr(SPRN_CTRLT, ctrl);
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}
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}
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static inline void ppc64_runlatch_off(void)
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{
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unsigned long ctrl;
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ctrl = mfspr(SPRN_CTRLF);
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ctrl &= ~CTRL_RUNLATCH;
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mtspr(SPRN_CTRLT, ctrl);
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if (cpu_has_feature(CPU_FTR_CTRL)) {
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ctrl = mfspr(SPRN_CTRLF);
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ctrl &= ~CTRL_RUNLATCH;
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mtspr(SPRN_CTRLT, ctrl);
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}
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}
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#endif /* __KERNEL__ */
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