vfio-pci: Allow mapping MSIX BAR
By default VFIO disables mapping of MSIX BAR to the userspace as the userspace may program it in a way allowing spurious interrupts; instead the userspace uses the VFIO_DEVICE_SET_IRQS ioctl. In order to eliminate guessing from the userspace about what is mmapable, VFIO also advertises a sparse list of regions allowed to mmap. This works fine as long as the system page size equals to the MSIX alignment requirement which is 4KB. However with a bigger page size the existing code prohibits mapping non-MSIX parts of a page with MSIX structures so these parts have to be emulated via slow reads/writes on a VFIO device fd. If these emulated bits are accessed often, this has serious impact on performance. This allows mmap of the entire BAR containing MSIX vector table. This removes the sparse capability for PCI devices as it becomes useless. As the userspace needs to know for sure whether mmapping of the MSIX vector containing data can succeed, this adds a new capability - VFIO_REGION_INFO_CAP_MSIX_MAPPABLE - which explicitly tells the userspace that the entire BAR can be mmapped. This does not touch the MSIX mangling in the BAR read/write handlers as we are doing this just to enable direct access to non MSIX registers. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [aw - fixup whitespace, trim function name] Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
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@ -565,47 +565,15 @@ static int vfio_pci_for_each_slot_or_bus(struct pci_dev *pdev,
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return walk.ret;
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}
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static int msix_sparse_mmap_cap(struct vfio_pci_device *vdev,
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struct vfio_info_cap *caps)
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static int msix_mmappable_cap(struct vfio_pci_device *vdev,
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struct vfio_info_cap *caps)
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{
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struct vfio_region_info_cap_sparse_mmap *sparse;
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size_t end, size;
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int nr_areas = 2, i = 0, ret;
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struct vfio_info_cap_header header = {
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.id = VFIO_REGION_INFO_CAP_MSIX_MAPPABLE,
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.version = 1
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};
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end = pci_resource_len(vdev->pdev, vdev->msix_bar);
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/* If MSI-X table is aligned to the start or end, only one area */
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if (((vdev->msix_offset & PAGE_MASK) == 0) ||
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(PAGE_ALIGN(vdev->msix_offset + vdev->msix_size) >= end))
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nr_areas = 1;
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size = sizeof(*sparse) + (nr_areas * sizeof(*sparse->areas));
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sparse = kzalloc(size, GFP_KERNEL);
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if (!sparse)
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return -ENOMEM;
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sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP;
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sparse->header.version = 1;
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sparse->nr_areas = nr_areas;
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if (vdev->msix_offset & PAGE_MASK) {
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sparse->areas[i].offset = 0;
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sparse->areas[i].size = vdev->msix_offset & PAGE_MASK;
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i++;
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}
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if (PAGE_ALIGN(vdev->msix_offset + vdev->msix_size) < end) {
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sparse->areas[i].offset = PAGE_ALIGN(vdev->msix_offset +
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vdev->msix_size);
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sparse->areas[i].size = end - sparse->areas[i].offset;
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i++;
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}
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ret = vfio_info_add_capability(caps, &sparse->header, size);
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kfree(sparse);
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return ret;
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return vfio_info_add_capability(caps, &header, sizeof(header));
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}
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int vfio_pci_register_dev_region(struct vfio_pci_device *vdev,
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@ -696,7 +664,7 @@ static long vfio_pci_ioctl(void *device_data,
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if (vdev->bar_mmap_supported[info.index]) {
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info.flags |= VFIO_REGION_INFO_FLAG_MMAP;
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if (info.index == vdev->msix_bar) {
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ret = msix_sparse_mmap_cap(vdev, &caps);
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ret = msix_mmappable_cap(vdev, &caps);
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if (ret)
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return ret;
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}
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@ -1127,22 +1095,6 @@ static int vfio_pci_mmap(void *device_data, struct vm_area_struct *vma)
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if (req_start + req_len > phys_len)
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return -EINVAL;
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if (index == vdev->msix_bar) {
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/*
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* Disallow mmaps overlapping the MSI-X table; users don't
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* get to touch this directly. We could find somewhere
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* else to map the overlap, but page granularity is only
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* a recommendation, not a requirement, so the user needs
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* to know which bits are real. Requiring them to mmap
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* around the table makes that clear.
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*/
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/* If neither entirely above nor below, then it overlaps */
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if (!(req_start >= vdev->msix_offset + vdev->msix_size ||
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req_start + req_len <= vdev->msix_offset))
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return -EINVAL;
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}
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/*
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* Even though we don't make use of the barmap for the mmap,
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* we need to request the region and the barmap tracks that.
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@ -301,6 +301,16 @@ struct vfio_region_info_cap_type {
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#define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2)
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#define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3)
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/*
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* The MSIX mappable capability informs that MSIX data of a BAR can be mmapped
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* which allows direct access to non-MSIX registers which happened to be within
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* the same system page.
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*
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* Even though the userspace gets direct access to the MSIX data, the existing
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* VFIO_DEVICE_SET_IRQS interface must still be used for MSIX configuration.
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*/
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#define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3
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/**
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* VFIO_DEVICE_GET_IRQ_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 9,
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* struct vfio_irq_info)
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