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MLK-16841-1: dma: imx-sdma: add clock ration 1:1 check 

On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted,
since SDMA clock ration has to be increased to 250Mhz, AHB can't reach
to 500Mhz, so use 1:1 instead.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
pull/10/head
Robin Gong 2017-11-16 17:23:40 +08:00 committed by Jason Liu
parent ffa3d9eda4
commit a328859d81
2 changed files with 9 additions and 1 deletions
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1
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
View File

@ -69,6 +69,7 @@ Optional properties:
reg is the GPR register offset.
shift is the bit position inside the GPR register.
val is the value of the bit (0 or 1).
- fsl,ratio-1-1: AHB/SDMA core clock ration 1:1, 2:1 without this.
Examples:

9
drivers/dma/imx-sdma.c
View File

@ -426,6 +426,8 @@ struct sdma_engine {
struct sdma_buffer_descriptor *bd0;
bool suspend_off;
int idx;
/* clock ration for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
bool clk_ratio;
};
static struct sdma_driver_data sdma_imx31 = {
@ -2107,7 +2109,10 @@ static int sdma_init(struct sdma_engine *sdma)
/* Set bits of CONFIG register but with static context switching */
/* FIXME: Check whether to set ACR bit depending on clock ratios */
writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
if (sdma->clk_ratio)
writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
else
writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
@ -2200,6 +2205,8 @@ static int sdma_probe(struct platform_device *pdev)
if (!sdma)
return -ENOMEM;
sdma->clk_ratio = of_property_read_bool(np, "fsl,ratio-1-1");
spin_lock_init(&sdma->channel_0_lock);
sdma->dev = &pdev->dev;