Merge remote-tracking branch 'spi/topic/sirf' into spi-next
This commit is contained in:
commit
a3e412dcf5
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@ -433,7 +433,7 @@ config SPI_SH_HSPI
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config SPI_SIRF
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tristate "CSR SiRFprimaII SPI controller"
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depends on ARCH_SIRF
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depends on SIRF_DMA
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select SPI_BITBANG
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help
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SPI driver for CSR SiRFprimaII SoCs
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@ -19,6 +19,10 @@
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#include <linux/of_gpio.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-direction.h>
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#include <linux/dma-mapping.h>
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#include <linux/sirfsoc_dma.h>
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#define DRIVER_NAME "sirfsoc_spi"
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@ -119,9 +123,19 @@
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#define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20)
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#define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2)
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/*
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* only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
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* due to the limitation of dma controller
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*/
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#define ALIGNED(x) (!((u32)x & 0x3))
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#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
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ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
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struct sirfsoc_spi {
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struct spi_bitbang bitbang;
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struct completion done;
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struct completion rx_done;
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struct completion tx_done;
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void __iomem *base;
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u32 ctrl_freq; /* SPI controller clock speed */
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@ -137,8 +151,16 @@ struct sirfsoc_spi {
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void (*tx_word) (struct sirfsoc_spi *);
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/* number of words left to be tranmitted/received */
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unsigned int left_tx_cnt;
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unsigned int left_rx_cnt;
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unsigned int left_tx_word;
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unsigned int left_rx_word;
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/* rx & tx DMA channels */
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struct dma_chan *rx_chan;
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struct dma_chan *tx_chan;
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dma_addr_t src_start;
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dma_addr_t dst_start;
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void *dummypage;
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int word_width; /* in bytes */
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int chipselect[0];
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};
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@ -155,7 +177,7 @@ static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
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sspi->rx = rx;
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}
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sspi->left_rx_cnt--;
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sspi->left_rx_word--;
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}
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static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
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@ -169,7 +191,7 @@ static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
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}
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writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
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sspi->left_tx_cnt--;
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sspi->left_tx_word--;
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}
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static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
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@ -184,7 +206,7 @@ static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
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sspi->rx = rx;
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}
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sspi->left_rx_cnt--;
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sspi->left_rx_word--;
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}
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static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
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@ -198,7 +220,7 @@ static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
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}
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writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
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sspi->left_tx_cnt--;
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sspi->left_tx_word--;
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}
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static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
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@ -213,7 +235,7 @@ static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
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sspi->rx = rx;
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}
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sspi->left_rx_cnt--;
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sspi->left_rx_word--;
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}
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@ -228,7 +250,7 @@ static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
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}
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writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
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sspi->left_tx_cnt--;
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sspi->left_tx_word--;
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}
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static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
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@ -241,7 +263,7 @@ static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
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/* Error Conditions */
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if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
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spi_stat & SIRFSOC_SPI_TX_UFLOW) {
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complete(&sspi->done);
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complete(&sspi->rx_done);
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writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
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}
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@ -249,50 +271,61 @@ static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
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| SIRFSOC_SPI_RXFIFO_THD_REACH))
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while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
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& SIRFSOC_SPI_FIFO_EMPTY)) &&
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sspi->left_rx_cnt)
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sspi->left_rx_word)
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sspi->rx_word(sspi);
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if (spi_stat & (SIRFSOC_SPI_FIFO_EMPTY
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| SIRFSOC_SPI_TXFIFO_THD_REACH))
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while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
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& SIRFSOC_SPI_FIFO_FULL)) &&
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sspi->left_tx_cnt)
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sspi->left_tx_word)
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sspi->tx_word(sspi);
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/* Received all words */
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if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
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complete(&sspi->done);
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if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) {
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complete(&sspi->rx_done);
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writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
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}
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return IRQ_HANDLED;
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}
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static void spi_sirfsoc_dma_fini_callback(void *data)
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{
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struct completion *dma_complete = data;
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complete(dma_complete);
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}
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static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct sirfsoc_spi *sspi;
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int timeout = t->len * 10;
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sspi = spi_master_get_devdata(spi->master);
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sspi->tx = t->tx_buf;
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sspi->rx = t->rx_buf;
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sspi->left_tx_cnt = sspi->left_rx_cnt = t->len;
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INIT_COMPLETION(sspi->done);
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sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
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sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
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sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
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INIT_COMPLETION(sspi->rx_done);
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INIT_COMPLETION(sspi->tx_done);
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writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
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if (t->len == 1) {
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if (sspi->left_tx_word == 1) {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
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SIRFSOC_SPI_ENA_AUTO_CLR,
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sspi->base + SIRFSOC_SPI_CTRL);
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writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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} else if ((t->len > 1) && (t->len < SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
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} else if ((sspi->left_tx_word > 1) && (sspi->left_tx_word <
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SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
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SIRFSOC_SPI_MUL_DAT_MODE |
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SIRFSOC_SPI_ENA_AUTO_CLR,
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sspi->base + SIRFSOC_SPI_CTRL);
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writel(t->len - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(t->len - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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writel(sspi->left_tx_word - 1,
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sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
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writel(sspi->left_tx_word - 1,
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sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
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} else {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
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sspi->base + SIRFSOC_SPI_CTRL);
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@ -305,17 +338,64 @@ static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
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/* Send the first word to trigger the whole tx/rx process */
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sspi->tx_word(sspi);
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if (IS_DMA_VALID(t)) {
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struct dma_async_tx_descriptor *rx_desc, *tx_desc;
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sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, DMA_FROM_DEVICE);
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rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
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sspi->dst_start, t->len, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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rx_desc->callback = spi_sirfsoc_dma_fini_callback;
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rx_desc->callback_param = &sspi->rx_done;
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sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, DMA_TO_DEVICE);
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tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
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sspi->src_start, t->len, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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tx_desc->callback = spi_sirfsoc_dma_fini_callback;
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tx_desc->callback_param = &sspi->tx_done;
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dmaengine_submit(tx_desc);
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dmaengine_submit(rx_desc);
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dma_async_issue_pending(sspi->tx_chan);
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dma_async_issue_pending(sspi->rx_chan);
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} else {
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/* Send the first word to trigger the whole tx/rx process */
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sspi->tx_word(sspi);
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writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
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SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
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SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
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SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
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}
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writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
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SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
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SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
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SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
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writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
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if (wait_for_completion_timeout(&sspi->done, timeout) == 0)
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if (!IS_DMA_VALID(t)) { /* for PIO */
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if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
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dev_err(&spi->dev, "transfer timeout\n");
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} else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
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dev_err(&spi->dev, "transfer timeout\n");
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dmaengine_terminate_all(sspi->rx_chan);
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} else
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sspi->left_rx_word = 0;
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/*
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* we only wait tx-done event if transferring by DMA. for PIO,
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* we get rx data by writing tx data, so if rx is done, tx has
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* done earlier
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*/
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if (IS_DMA_VALID(t)) {
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if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
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dev_err(&spi->dev, "transfer timeout\n");
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dmaengine_terminate_all(sspi->tx_chan);
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}
|
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}
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if (IS_DMA_VALID(t)) {
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dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
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dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
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}
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/* TX, RX FIFO stop */
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writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
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|
@ -323,7 +403,7 @@ static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
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writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
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writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
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return t->len - sspi->left_rx_cnt;
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return t->len - sspi->left_rx_word * sspi->word_width;
|
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}
|
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|
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static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
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|
@ -332,7 +412,6 @@ static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
|
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|
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if (sspi->chipselect[spi->chip_select] == 0) {
|
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u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
|
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regval |= SIRFSOC_SPI_CS_IO_OUT;
|
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switch (value) {
|
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case BITBANG_CS_ACTIVE:
|
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if (spi->mode & SPI_CS_HIGH)
|
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|
@ -369,11 +448,7 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
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bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
|
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hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
|
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|
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/* Enable IO mode for RX, TX */
|
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writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
|
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writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
|
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regval = (sspi->ctrl_freq / (2 * hz)) - 1;
|
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|
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if (regval > 0xFFFF || regval < 0) {
|
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dev_err(&spi->dev, "Speed %d not supported\n", hz);
|
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return -EINVAL;
|
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|
@ -388,6 +463,7 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
|||
SIRFSOC_SPI_FIFO_WIDTH_BYTE;
|
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rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
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SIRFSOC_SPI_FIFO_WIDTH_BYTE;
|
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sspi->word_width = 1;
|
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break;
|
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case 12:
|
||||
case 16:
|
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|
@ -399,6 +475,7 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
|||
SIRFSOC_SPI_FIFO_WIDTH_WORD;
|
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rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
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SIRFSOC_SPI_FIFO_WIDTH_WORD;
|
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sspi->word_width = 2;
|
||||
break;
|
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case 32:
|
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regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
|
||||
|
@ -408,6 +485,7 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
|||
SIRFSOC_SPI_FIFO_WIDTH_DWORD;
|
||||
rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
|
||||
SIRFSOC_SPI_FIFO_WIDTH_DWORD;
|
||||
sspi->word_width = 4;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
|
@ -442,6 +520,17 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
|
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writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
|
||||
|
||||
writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
|
||||
|
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if (IS_DMA_VALID(t)) {
|
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/* Enable DMA mode for RX, TX */
|
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writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
|
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writel(SIRFSOC_SPI_RX_DMA_FLUSH, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
|
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} else {
|
||||
/* Enable IO mode for RX, TX */
|
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writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
|
||||
writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -466,6 +555,8 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
|
|||
struct spi_master *master;
|
||||
struct resource *mem_res;
|
||||
int num_cs, cs_gpio, irq;
|
||||
u32 rx_dma_ch, tx_dma_ch;
|
||||
dma_cap_mask_t dma_cap_mask;
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
|
@ -476,6 +567,20 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
|
|||
goto err_cs;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node,
|
||||
"sirf,spi-dma-rx-channel", &rx_dma_ch);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Unable to get rx dma channel\n");
|
||||
goto err_cs;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node,
|
||||
"sirf,spi-dma-tx-channel", &tx_dma_ch);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Unable to get tx dma channel\n");
|
||||
goto err_cs;
|
||||
}
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
|
||||
if (!master) {
|
||||
dev_err(&pdev->dev, "Unable to allocate SPI master\n");
|
||||
|
@ -484,12 +589,6 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
|
|||
platform_set_drvdata(pdev, master);
|
||||
sspi = spi_master_get_devdata(master);
|
||||
|
||||
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem_res) {
|
||||
dev_err(&pdev->dev, "Unable to get IO resource\n");
|
||||
ret = -ENODEV;
|
||||
goto free_master;
|
||||
}
|
||||
master->num_chipselect = num_cs;
|
||||
|
||||
for (i = 0; i < master->num_chipselect; i++) {
|
||||
|
@ -516,6 +615,7 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
|
||||
if (IS_ERR(sspi->base)) {
|
||||
ret = PTR_ERR(sspi->base);
|
||||
|
@ -538,19 +638,40 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
|
|||
sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
|
||||
sspi->bitbang.master->setup = spi_sirfsoc_setup;
|
||||
master->bus_num = pdev->id;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
|
||||
SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
|
||||
sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
/* request DMA channels */
|
||||
dma_cap_zero(dma_cap_mask);
|
||||
dma_cap_set(DMA_INTERLEAVE, dma_cap_mask);
|
||||
|
||||
sspi->rx_chan = dma_request_channel(dma_cap_mask, (dma_filter_fn)sirfsoc_dma_filter_id,
|
||||
(void *)rx_dma_ch);
|
||||
if (!sspi->rx_chan) {
|
||||
dev_err(&pdev->dev, "can not allocate rx dma channel\n");
|
||||
ret = -ENODEV;
|
||||
goto free_master;
|
||||
}
|
||||
sspi->tx_chan = dma_request_channel(dma_cap_mask, (dma_filter_fn)sirfsoc_dma_filter_id,
|
||||
(void *)tx_dma_ch);
|
||||
if (!sspi->tx_chan) {
|
||||
dev_err(&pdev->dev, "can not allocate tx dma channel\n");
|
||||
ret = -ENODEV;
|
||||
goto free_rx_dma;
|
||||
}
|
||||
|
||||
sspi->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(sspi->clk)) {
|
||||
ret = -EINVAL;
|
||||
goto free_master;
|
||||
ret = PTR_ERR(sspi->clk);
|
||||
goto free_tx_dma;
|
||||
}
|
||||
clk_prepare_enable(sspi->clk);
|
||||
sspi->ctrl_freq = clk_get_rate(sspi->clk);
|
||||
|
||||
init_completion(&sspi->done);
|
||||
init_completion(&sspi->rx_done);
|
||||
init_completion(&sspi->tx_done);
|
||||
|
||||
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
|
||||
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
|
||||
|
@ -559,17 +680,28 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
|
|||
/* We are not using dummy delay between command and data */
|
||||
writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
|
||||
|
||||
sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL);
|
||||
if (!sspi->dummypage) {
|
||||
ret = -ENOMEM;
|
||||
goto free_clk;
|
||||
}
|
||||
|
||||
ret = spi_bitbang_start(&sspi->bitbang);
|
||||
if (ret)
|
||||
goto free_clk;
|
||||
goto free_dummypage;
|
||||
|
||||
dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
|
||||
|
||||
return 0;
|
||||
|
||||
free_dummypage:
|
||||
kfree(sspi->dummypage);
|
||||
free_clk:
|
||||
clk_disable_unprepare(sspi->clk);
|
||||
clk_put(sspi->clk);
|
||||
free_tx_dma:
|
||||
dma_release_channel(sspi->tx_chan);
|
||||
free_rx_dma:
|
||||
dma_release_channel(sspi->rx_chan);
|
||||
free_master:
|
||||
spi_master_put(master);
|
||||
err_cs:
|
||||
|
@ -590,8 +722,11 @@ static int spi_sirfsoc_remove(struct platform_device *pdev)
|
|||
if (sspi->chipselect[i] > 0)
|
||||
gpio_free(sspi->chipselect[i]);
|
||||
}
|
||||
kfree(sspi->dummypage);
|
||||
clk_disable_unprepare(sspi->clk);
|
||||
clk_put(sspi->clk);
|
||||
dma_release_channel(sspi->rx_chan);
|
||||
dma_release_channel(sspi->tx_chan);
|
||||
spi_master_put(master);
|
||||
return 0;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue