musb_gadget: fix unhandled endpoint 0 IRQs
The gadget EP0 code routinely ignores an interrupt at end of the data phase because of musb_g_ep0_giveback() resetting the state machine to "idle, waiting for SETUP" phase prematurely. The driver also prematurely leaves the status phase on receiving the SetupEnd interrupt. As there were still unhandled endpoint 0 interrupts happening from time to time after fixing these issues, there turned to be yet another culprit: two distinct gadget states collapsed into one. The (missing) state that comes after STATUS IN/OUT states was typically indiscernible from them since the corresponding interrupts tend to happen within too little period of time (due to only a zero-length status packet in between) and so they got coalesced; yet this state is not the same as the next one which is associated with the reception of a SETUP packet. Adding this extra state seems to have fixed the rest of the unhandled interrupts that generic_interrupt() and davinci_interrupt() hid by faking their result and only emitting a debug message -- so, stop doing that. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -372,12 +372,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
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spin_unlock_irqrestore(&musb->lock, flags);
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/* REVISIT we sometimes get unhandled IRQs
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* (e.g. ep0). not clear why...
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*/
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if (retval != IRQ_HANDLED)
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DBG(5, "unhandled? %08x\n", tmp);
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return IRQ_HANDLED;
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return retval;
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}
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int musb_platform_set_mode(struct musb *musb, u8 mode)
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@ -1481,13 +1481,7 @@ static irqreturn_t generic_interrupt(int irq, void *__hci)
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spin_unlock_irqrestore(&musb->lock, flags);
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/* REVISIT we sometimes get spurious IRQs on g_ep0
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* not clear why...
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*/
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if (retval != IRQ_HANDLED)
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DBG(5, "spurious?\n");
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return IRQ_HANDLED;
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return retval;
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}
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#else
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@ -171,7 +171,8 @@ enum musb_h_ep0_state {
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/* peripheral side ep0 states */
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enum musb_g_ep0_state {
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MUSB_EP0_STAGE_SETUP, /* idle, waiting for setup */
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MUSB_EP0_STAGE_IDLE, /* idle, waiting for SETUP */
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MUSB_EP0_STAGE_SETUP, /* received SETUP */
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MUSB_EP0_STAGE_TX, /* IN data */
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MUSB_EP0_STAGE_RX, /* OUT data */
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MUSB_EP0_STAGE_STATUSIN, /* (after OUT data) */
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@ -4,6 +4,7 @@
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* Copyright 2005 Mentor Graphics Corporation
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* Copyright (C) 2005-2006 by Texas Instruments
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* Copyright (C) 2006-2007 Nokia Corporation
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* Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -58,7 +59,8 @@
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static char *decode_ep0stage(u8 stage)
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{
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switch (stage) {
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case MUSB_EP0_STAGE_SETUP: return "idle";
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case MUSB_EP0_STAGE_IDLE: return "idle";
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case MUSB_EP0_STAGE_SETUP: return "setup";
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case MUSB_EP0_STAGE_TX: return "in";
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case MUSB_EP0_STAGE_RX: return "out";
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case MUSB_EP0_STAGE_ACKWAIT: return "wait";
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@ -628,7 +630,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
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musb_writew(regs, MUSB_CSR0,
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csr & ~MUSB_CSR0_P_SENTSTALL);
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retval = IRQ_HANDLED;
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musb->ep0_state = MUSB_EP0_STAGE_SETUP;
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musb->ep0_state = MUSB_EP0_STAGE_IDLE;
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csr = musb_readw(regs, MUSB_CSR0);
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}
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@ -636,7 +638,18 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
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if (csr & MUSB_CSR0_P_SETUPEND) {
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musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
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retval = IRQ_HANDLED;
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musb->ep0_state = MUSB_EP0_STAGE_SETUP;
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/* Transition into the early status phase */
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switch (musb->ep0_state) {
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case MUSB_EP0_STAGE_TX:
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musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
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break;
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case MUSB_EP0_STAGE_RX:
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musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
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break;
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default:
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ERR("SetupEnd came in a wrong ep0stage %s",
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decode_ep0stage(musb->ep0_state));
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}
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csr = musb_readw(regs, MUSB_CSR0);
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/* NOTE: request may need completion */
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}
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@ -697,11 +710,31 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
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if (req)
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musb_g_ep0_giveback(musb, req);
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}
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/*
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* In case when several interrupts can get coalesced,
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* check to see if we've already received a SETUP packet...
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*/
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if (csr & MUSB_CSR0_RXPKTRDY)
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goto setup;
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retval = IRQ_HANDLED;
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musb->ep0_state = MUSB_EP0_STAGE_IDLE;
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break;
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case MUSB_EP0_STAGE_IDLE:
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/*
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* This state is typically (but not always) indiscernible
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* from the status states since the corresponding interrupts
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* tend to happen within too little period of time (with only
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* a zero-length packet in between) and so get coalesced...
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*/
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retval = IRQ_HANDLED;
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musb->ep0_state = MUSB_EP0_STAGE_SETUP;
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/* FALLTHROUGH */
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case MUSB_EP0_STAGE_SETUP:
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setup:
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if (csr & MUSB_CSR0_RXPKTRDY) {
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struct usb_ctrlrequest setup;
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int handled = 0;
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@ -783,7 +816,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
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stall:
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DBG(3, "stall (%d)\n", handled);
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musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
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musb->ep0_state = MUSB_EP0_STAGE_SETUP;
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musb->ep0_state = MUSB_EP0_STAGE_IDLE;
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finish:
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musb_writew(regs, MUSB_CSR0,
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musb->ackpend);
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@ -803,7 +836,7 @@ finish:
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/* "can't happen" */
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WARN_ON(1);
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musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
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musb->ep0_state = MUSB_EP0_STAGE_SETUP;
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musb->ep0_state = MUSB_EP0_STAGE_IDLE;
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break;
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}
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@ -959,7 +992,7 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
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csr |= MUSB_CSR0_P_SENDSTALL;
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musb_writew(regs, MUSB_CSR0, csr);
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musb->ep0_state = MUSB_EP0_STAGE_SETUP;
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musb->ep0_state = MUSB_EP0_STAGE_IDLE;
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musb->ackpend = 0;
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break;
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default:
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