arm64: Handle erratum 1418040
as a superset of erratum 1188873
We already mitigate erratum 1188873 affecting Cortex-A76 and Neoverse-N1 r0p0 to r2p0. It turns out that revisions r0p0 to r3p1 of the same cores are affected by erratum1418040
, which has the same workaround as 1188873. Let's expand the range of affected revisions to match1418040
, and repaint all occurences of 1188873 to1418040
. Whilst we're there, do a bit of reformating in silicon-errata.txt and drop a now unnecessary dependency on ARM_ARCH_TIMER_OOL_WORKAROUND. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -58,14 +58,14 @@ stable kernels.
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| ARM | Cortex-A72 | #853709 | N/A |
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| ARM | Cortex-A72 | #853709 | N/A |
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
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| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
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| ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 |
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| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
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| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
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| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
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| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
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| ARM | Neoverse-N1 | #1188873 | ARM64_ERRATUM_1188873 |
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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| ARM | MMU-500 | #841119,#826419 | N/A |
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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| ARM | MMU-500 | #841119,826419 | N/A |
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| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
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| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
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| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
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| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
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| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
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| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
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@ -475,16 +475,15 @@ config ARM64_ERRATUM_1024718
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If unsure, say Y.
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If unsure, say Y.
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config ARM64_ERRATUM_1188873
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config ARM64_ERRATUM_1418040
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bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
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bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
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default y
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default y
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depends on COMPAT
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depends on COMPAT
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select ARM_ARCH_TIMER_OOL_WORKAROUND
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help
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help
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This option adds a workaround for ARM Cortex-A76/Neoverse-N1
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This option adds a workaround for ARM Cortex-A76/Neoverse-N1
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erratum 1188873.
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errata 1188873 and 1418040.
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Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could
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Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
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cause register corruption when accessing the timer registers
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cause register corruption when accessing the timer registers
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from AArch32 userspace.
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from AArch32 userspace.
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@ -53,7 +53,7 @@
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#define ARM64_HAS_STAGE2_FWB 32
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#define ARM64_HAS_STAGE2_FWB 32
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#define ARM64_HAS_CRC32 33
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#define ARM64_HAS_CRC32 33
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#define ARM64_SSBS 34
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#define ARM64_SSBS 34
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#define ARM64_WORKAROUND_1188873 35
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#define ARM64_WORKAROUND_1418040 35
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#define ARM64_HAS_SB 36
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#define ARM64_HAS_SB 36
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#define ARM64_WORKAROUND_1165522 37
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#define ARM64_WORKAROUND_1165522 37
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#define ARM64_HAS_ADDRESS_AUTH_ARCH 38
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#define ARM64_HAS_ADDRESS_AUTH_ARCH 38
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@ -698,12 +698,16 @@ static const struct midr_range workaround_clean_cache[] = {
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};
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};
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#endif
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1188873
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#ifdef CONFIG_ARM64_ERRATUM_1418040
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static const struct midr_range erratum_1188873_list[] = {
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/*
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/* Cortex-A76 r0p0 to r2p0 */
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* - 1188873 affects r0p0 to r2p0
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
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* - 1418040 affects r0p0 to r3p1
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/* Neoverse-N1 r0p0 to r2p0 */
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*/
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MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0),
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static const struct midr_range erratum_1418040_list[] = {
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/* Cortex-A76 r0p0 to r3p1 */
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
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/* Neoverse-N1 r0p0 to r3p1 */
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MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
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{},
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{},
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};
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};
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#endif
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#endif
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@ -825,11 +829,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.matches = has_ssbd_mitigation,
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.matches = has_ssbd_mitigation,
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.midr_range_list = arm64_ssb_cpus,
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.midr_range_list = arm64_ssb_cpus,
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},
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},
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#ifdef CONFIG_ARM64_ERRATUM_1188873
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#ifdef CONFIG_ARM64_ERRATUM_1418040
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{
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{
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.desc = "ARM erratum 1188873",
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.desc = "ARM erratum 1418040",
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.capability = ARM64_WORKAROUND_1188873,
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.capability = ARM64_WORKAROUND_1418040,
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ERRATA_MIDR_RANGE_LIST(erratum_1188873_list),
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ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
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},
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},
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#endif
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1165522
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#ifdef CONFIG_ARM64_ERRATUM_1165522
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@ -336,8 +336,8 @@ alternative_if ARM64_WORKAROUND_845719
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alternative_else_nop_endif
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alternative_else_nop_endif
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#endif
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#endif
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3:
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3:
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#ifdef CONFIG_ARM64_ERRATUM_1188873
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#ifdef CONFIG_ARM64_ERRATUM_1418040
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alternative_if_not ARM64_WORKAROUND_1188873
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alternative_if_not ARM64_WORKAROUND_1418040
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b 4f
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b 4f
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alternative_else_nop_endif
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alternative_else_nop_endif
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/*
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/*
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