powerpc: Separate out load/store emulation into its own function
This moves the parts of emulate_step() that deal with emulating load and store instructions into a new function called emulate_loadstore(). This is to make it possible to reuse this code in the alignment handler. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>zero-colors
Paul Mackerras
Michael Ellerman
parent
d955189ae4
commit
a53d5182e2
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@ -152,6 +152,15 @@ void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op);
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*/
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extern int emulate_step(struct pt_regs *regs, unsigned int instr);
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/*
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* Emulate a load or store instruction by reading/writing the
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* memory of the current process. FP/VMX/VSX registers are assumed
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* to hold live values if the appropriate enable bit in regs->msr is
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* set; otherwise this will use the saved values in the thread struct
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* for user-mode accesses.
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*/
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extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op);
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extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
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const void *mem, bool cross_endian);
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extern void emulate_vsx_store(struct instruction_op *op,
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@ -2666,6 +2666,262 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
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regs->nip = next_pc;
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}
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/*
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* Emulate a previously-analysed load or store instruction.
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* Return values are:
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* 0 = instruction emulated successfully
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* -EFAULT = address out of range or access faulted (regs->dar
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* contains the faulting address)
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* -EACCES = misaligned access, instruction requires alignment
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* -EINVAL = unknown operation in *op
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*/
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int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
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{
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int err, size, type;
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int i, rd, nb;
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unsigned int cr;
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unsigned long val;
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unsigned long ea;
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bool cross_endian;
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err = 0;
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size = GETSIZE(op->type);
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type = op->type & INSTR_TYPE_MASK;
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cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
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ea = truncate_if_32bit(regs->msr, op->ea);
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switch (type) {
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case LARX:
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if (ea & (size - 1))
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return -EACCES; /* can't handle misaligned */
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if (!address_ok(regs, ea, size))
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return -EFAULT;
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err = 0;
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switch (size) {
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#ifdef __powerpc64__
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case 1:
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__get_user_asmx(val, ea, err, "lbarx");
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break;
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case 2:
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__get_user_asmx(val, ea, err, "lharx");
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break;
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#endif
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case 4:
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__get_user_asmx(val, ea, err, "lwarx");
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break;
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#ifdef __powerpc64__
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case 8:
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__get_user_asmx(val, ea, err, "ldarx");
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break;
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case 16:
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err = do_lqarx(ea, ®s->gpr[op->reg]);
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break;
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#endif
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default:
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return -EINVAL;
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}
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if (err) {
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regs->dar = ea;
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break;
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}
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if (size < 16)
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regs->gpr[op->reg] = val;
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break;
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case STCX:
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if (ea & (size - 1))
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return -EACCES; /* can't handle misaligned */
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if (!address_ok(regs, ea, size))
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return -EFAULT;
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err = 0;
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switch (size) {
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#ifdef __powerpc64__
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case 1:
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__put_user_asmx(op->val, ea, err, "stbcx.", cr);
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break;
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case 2:
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__put_user_asmx(op->val, ea, err, "stbcx.", cr);
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break;
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#endif
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case 4:
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__put_user_asmx(op->val, ea, err, "stwcx.", cr);
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break;
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#ifdef __powerpc64__
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case 8:
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__put_user_asmx(op->val, ea, err, "stdcx.", cr);
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break;
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case 16:
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err = do_stqcx(ea, regs->gpr[op->reg],
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regs->gpr[op->reg + 1], &cr);
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break;
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#endif
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default:
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return -EINVAL;
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}
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if (!err)
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regs->ccr = (regs->ccr & 0x0fffffff) |
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(cr & 0xe0000000) |
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((regs->xer >> 3) & 0x10000000);
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else
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regs->dar = ea;
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break;
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case LOAD:
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#ifdef __powerpc64__
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if (size == 16) {
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err = emulate_lq(regs, ea, op->reg, cross_endian);
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break;
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}
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#endif
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err = read_mem(®s->gpr[op->reg], ea, size, regs);
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if (!err) {
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if (op->type & SIGNEXT)
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do_signext(®s->gpr[op->reg], size);
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if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
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do_byterev(®s->gpr[op->reg], size);
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}
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break;
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#ifdef CONFIG_PPC_FPU
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case LOAD_FP:
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/*
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* If the instruction is in userspace, we can emulate it even
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* if the VMX state is not live, because we have the state
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* stored in the thread_struct. If the instruction is in
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* the kernel, we must not touch the state in the thread_struct.
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*/
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if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
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return 0;
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err = do_fp_load(op->reg, ea, size, regs, cross_endian);
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break;
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#endif
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#ifdef CONFIG_ALTIVEC
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case LOAD_VMX:
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if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
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return 0;
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err = do_vec_load(op->reg, ea, size, regs, cross_endian);
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break;
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#endif
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#ifdef CONFIG_VSX
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case LOAD_VSX: {
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unsigned long msrbit = MSR_VSX;
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/*
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* Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
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* when the target of the instruction is a vector register.
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*/
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if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
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msrbit = MSR_VEC;
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if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
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return 0;
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err = do_vsx_load(op, ea, regs, cross_endian);
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break;
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}
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#endif
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case LOAD_MULTI:
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if (!address_ok(regs, ea, size))
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return -EFAULT;
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rd = op->reg;
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for (i = 0; i < size; i += 4) {
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unsigned int v32 = 0;
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nb = size - i;
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if (nb > 4)
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nb = 4;
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err = copy_mem_in((u8 *) &v32, ea, nb, regs);
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if (err)
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break;
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if (unlikely(cross_endian))
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v32 = byterev_4(v32);
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regs->gpr[rd] = v32;
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ea += 4;
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++rd;
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}
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break;
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case STORE:
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#ifdef __powerpc64__
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if (size == 16) {
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err = emulate_stq(regs, ea, op->reg, cross_endian);
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break;
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}
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#endif
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if ((op->type & UPDATE) && size == sizeof(long) &&
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op->reg == 1 && op->update_reg == 1 &&
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!(regs->msr & MSR_PR) &&
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ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
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err = handle_stack_update(ea, regs);
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break;
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}
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if (unlikely(cross_endian))
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do_byterev(&op->val, size);
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err = write_mem(op->val, ea, size, regs);
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break;
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#ifdef CONFIG_PPC_FPU
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case STORE_FP:
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if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
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return 0;
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err = do_fp_store(op->reg, ea, size, regs, cross_endian);
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break;
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#endif
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#ifdef CONFIG_ALTIVEC
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case STORE_VMX:
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if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
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return 0;
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err = do_vec_store(op->reg, ea, size, regs, cross_endian);
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break;
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#endif
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#ifdef CONFIG_VSX
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case STORE_VSX: {
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unsigned long msrbit = MSR_VSX;
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/*
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* Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
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* when the target of the instruction is a vector register.
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*/
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if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
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msrbit = MSR_VEC;
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if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
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return 0;
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err = do_vsx_store(op, ea, regs, cross_endian);
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break;
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}
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#endif
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case STORE_MULTI:
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if (!address_ok(regs, ea, size))
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return -EFAULT;
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rd = op->reg;
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for (i = 0; i < size; i += 4) {
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unsigned int v32 = regs->gpr[rd];
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nb = size - i;
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if (nb > 4)
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nb = 4;
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if (unlikely(cross_endian))
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v32 = byterev_4(v32);
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err = copy_mem_out((u8 *) &v32, ea, nb, regs);
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if (err)
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break;
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ea += 4;
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++rd;
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}
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break;
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default:
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return -EINVAL;
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}
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if (err)
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return err;
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if (op->type & UPDATE)
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regs->gpr[op->update_reg] = op->ea;
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return 0;
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}
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NOKPROBE_SYMBOL(emulate_loadstore);
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/*
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* Emulate instructions that cause a transfer of control,
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* loads and stores, and a few other instructions.
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@ -2676,12 +2932,9 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
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int emulate_step(struct pt_regs *regs, unsigned int instr)
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{
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struct instruction_op op;
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int r, err, size, type;
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int r, err, type;
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unsigned long val;
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unsigned int cr;
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int i, rd, nb;
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unsigned long ea;
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bool cross_endian;
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r = analyse_instr(&op, regs, instr);
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if (r < 0)
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@ -2692,16 +2945,18 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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}
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err = 0;
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size = GETSIZE(op.type);
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type = op.type & INSTR_TYPE_MASK;
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cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
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ea = op.ea;
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if (OP_IS_LOAD_STORE(type) || type == CACHEOP)
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ea = truncate_if_32bit(regs->msr, op.ea);
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if (OP_IS_LOAD_STORE(type)) {
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err = emulate_loadstore(regs, &op);
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if (err)
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return 0;
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goto instr_done;
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}
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switch (type) {
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case CACHEOP:
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ea = truncate_if_32bit(regs->msr, op.ea);
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if (!address_ok(regs, ea, 8))
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return 0;
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switch (op.type & CACHEOP_MASK) {
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@ -2732,223 +2987,6 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
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}
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goto instr_done;
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case LARX:
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if (ea & (size - 1))
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break; /* can't handle misaligned */
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if (!address_ok(regs, ea, size))
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return 0;
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err = 0;
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switch (size) {
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#ifdef __powerpc64__
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case 1:
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__get_user_asmx(val, ea, err, "lbarx");
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break;
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case 2:
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__get_user_asmx(val, ea, err, "lharx");
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break;
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#endif
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case 4:
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__get_user_asmx(val, ea, err, "lwarx");
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break;
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#ifdef __powerpc64__
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case 8:
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__get_user_asmx(val, ea, err, "ldarx");
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break;
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case 16:
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err = do_lqarx(ea, ®s->gpr[op.reg]);
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break;
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#endif
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default:
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return 0;
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}
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if (err) {
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regs->dar = ea;
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return 0;
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}
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if (size < 16)
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regs->gpr[op.reg] = val;
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goto ldst_done;
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case STCX:
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if (ea & (size - 1))
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break; /* can't handle misaligned */
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if (!address_ok(regs, ea, size))
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return 0;
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err = 0;
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switch (size) {
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#ifdef __powerpc64__
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case 1:
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__put_user_asmx(op.val, ea, err, "stbcx.", cr);
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break;
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case 2:
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__put_user_asmx(op.val, ea, err, "stbcx.", cr);
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break;
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#endif
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case 4:
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__put_user_asmx(op.val, ea, err, "stwcx.", cr);
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break;
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#ifdef __powerpc64__
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case 8:
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__put_user_asmx(op.val, ea, err, "stdcx.", cr);
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break;
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case 16:
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err = do_stqcx(ea, regs->gpr[op.reg],
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regs->gpr[op.reg + 1], &cr);
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break;
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#endif
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default:
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return 0;
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}
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if (!err)
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regs->ccr = (regs->ccr & 0x0fffffff) |
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(cr & 0xe0000000) |
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((regs->xer >> 3) & 0x10000000);
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else
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regs->dar = ea;
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goto ldst_done;
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case LOAD:
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#ifdef __powerpc64__
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if (size == 16) {
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err = emulate_lq(regs, ea, op.reg, cross_endian);
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goto ldst_done;
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}
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#endif
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err = read_mem(®s->gpr[op.reg], ea, size, regs);
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if (!err) {
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if (op.type & SIGNEXT)
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do_signext(®s->gpr[op.reg], size);
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if ((op.type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
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do_byterev(®s->gpr[op.reg], size);
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}
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goto ldst_done;
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#ifdef CONFIG_PPC_FPU
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case LOAD_FP:
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/*
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* If the instruction is in userspace, we can emulate it even
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* if the VMX state is not live, because we have the state
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* stored in the thread_struct. If the instruction is in
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* the kernel, we must not touch the state in the thread_struct.
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*/
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if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
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return 0;
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err = do_fp_load(op.reg, ea, size, regs, cross_endian);
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goto ldst_done;
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#endif
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#ifdef CONFIG_ALTIVEC
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case LOAD_VMX:
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if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
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return 0;
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err = do_vec_load(op.reg, ea, size, regs, cross_endian);
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goto ldst_done;
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#endif
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#ifdef CONFIG_VSX
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case LOAD_VSX: {
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unsigned long msrbit = MSR_VSX;
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/*
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* Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
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* when the target of the instruction is a vector register.
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*/
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if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC))
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msrbit = MSR_VEC;
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if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
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return 0;
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err = do_vsx_load(&op, ea, regs, cross_endian);
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goto ldst_done;
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}
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#endif
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case LOAD_MULTI:
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if (!address_ok(regs, ea, size))
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return -EFAULT;
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rd = op.reg;
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for (i = 0; i < size; i += 4) {
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unsigned int v32 = 0;
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nb = size - i;
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if (nb > 4)
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nb = 4;
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err = copy_mem_in((u8 *) &v32, ea, nb, regs);
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if (err)
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return 0;
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if (unlikely(cross_endian))
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v32 = byterev_4(v32);
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regs->gpr[rd] = v32;
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ea += 4;
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++rd;
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}
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goto instr_done;
|
||||
|
||||
case STORE:
|
||||
#ifdef __powerpc64__
|
||||
if (size == 16) {
|
||||
err = emulate_stq(regs, ea, op.reg, cross_endian);
|
||||
goto ldst_done;
|
||||
}
|
||||
#endif
|
||||
if ((op.type & UPDATE) && size == sizeof(long) &&
|
||||
op.reg == 1 && op.update_reg == 1 &&
|
||||
!(regs->msr & MSR_PR) &&
|
||||
ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
|
||||
err = handle_stack_update(ea, regs);
|
||||
goto ldst_done;
|
||||
}
|
||||
if (unlikely(cross_endian))
|
||||
do_byterev(&op.val, size);
|
||||
err = write_mem(op.val, ea, size, regs);
|
||||
goto ldst_done;
|
||||
|
||||
#ifdef CONFIG_PPC_FPU
|
||||
case STORE_FP:
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
|
||||
return 0;
|
||||
err = do_fp_store(op.reg, ea, size, regs, cross_endian);
|
||||
goto ldst_done;
|
||||
#endif
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
case STORE_VMX:
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
|
||||
return 0;
|
||||
err = do_vec_store(op.reg, ea, size, regs, cross_endian);
|
||||
goto ldst_done;
|
||||
#endif
|
||||
#ifdef CONFIG_VSX
|
||||
case STORE_VSX: {
|
||||
unsigned long msrbit = MSR_VSX;
|
||||
|
||||
/*
|
||||
* Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
|
||||
* when the target of the instruction is a vector register.
|
||||
*/
|
||||
if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC))
|
||||
msrbit = MSR_VEC;
|
||||
if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
|
||||
return 0;
|
||||
err = do_vsx_store(&op, ea, regs, cross_endian);
|
||||
goto ldst_done;
|
||||
}
|
||||
#endif
|
||||
case STORE_MULTI:
|
||||
if (!address_ok(regs, ea, size))
|
||||
return -EFAULT;
|
||||
rd = op.reg;
|
||||
for (i = 0; i < size; i += 4) {
|
||||
unsigned int v32 = regs->gpr[rd];
|
||||
|
||||
nb = size - i;
|
||||
if (nb > 4)
|
||||
nb = 4;
|
||||
if (unlikely(cross_endian))
|
||||
v32 = byterev_4(v32);
|
||||
err = copy_mem_out((u8 *) &v32, ea, nb, regs);
|
||||
if (err)
|
||||
return 0;
|
||||
ea += 4;
|
||||
++rd;
|
||||
}
|
||||
goto instr_done;
|
||||
|
||||
case MFMSR:
|
||||
regs->gpr[op.reg] = regs->msr & MSR_MASK;
|
||||
goto instr_done;
|
||||
|
|
@ -2989,12 +3027,6 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)
|
|||
}
|
||||
return 0;
|
||||
|
||||
ldst_done:
|
||||
if (err)
|
||||
return 0;
|
||||
if (op.type & UPDATE)
|
||||
regs->gpr[op.update_reg] = op.ea;
|
||||
|
||||
instr_done:
|
||||
regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
|
||||
return 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue