Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: OMAP3: PM: ensure IO wakeups are properly disabled omap: Fix omap_4430sdp_defconfig for make oldconfig omap: Use CONFIG_SMP for test_for_ipi and test_for_ltirq omap: Fix sev instruction usage for multi-omap OMAP3: Fix a cpu type check problem omap3: id: fix 3630 rev detection
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commit
a5a8283495
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@ -13,6 +13,9 @@ CONFIG_MODULE_SRCVERSION_ALL=y
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_ARCH_OMAP=y
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CONFIG_ARCH_OMAP=y
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CONFIG_ARCH_OMAP4=y
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CONFIG_ARCH_OMAP4=y
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# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
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# CONFIG_ARCH_OMAP2 is not set
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# CONFIG_ARCH_OMAP3 is not set
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# CONFIG_OMAP_MUX is not set
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# CONFIG_OMAP_MUX is not set
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CONFIG_OMAP_32K_TIMER=y
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CONFIG_OMAP_32K_TIMER=y
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CONFIG_OMAP_DM_TIMER=y
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CONFIG_OMAP_DM_TIMER=y
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@ -25,6 +25,7 @@ obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
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obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
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obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
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obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
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obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
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AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a
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AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
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AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
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# Functions loaded to SRAM
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# Functions loaded to SRAM
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@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void)
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struct omap_clk *c;
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struct omap_clk *c;
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u32 cpu_clkflg = CK_3XXX;
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u32 cpu_clkflg = CK_3XXX;
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if (cpu_is_omap34xx()) {
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if (cpu_is_omap3517()) {
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cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
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cpu_clkflg |= CK_3517;
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} else if (cpu_is_omap3505()) {
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cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
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cpu_clkflg |= CK_3505;
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} else if (cpu_is_omap34xx()) {
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cpu_mask = RATE_IN_3XXX;
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cpu_mask = RATE_IN_3XXX;
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cpu_clkflg |= CK_343X;
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cpu_clkflg |= CK_343X;
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@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void)
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cpu_mask |= RATE_IN_3430ES2PLUS;
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cpu_mask |= RATE_IN_3430ES2PLUS;
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cpu_clkflg |= CK_3430ES2;
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cpu_clkflg |= CK_3430ES2;
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}
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}
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} else if (cpu_is_omap3517()) {
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cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
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cpu_clkflg |= CK_3517;
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} else if (cpu_is_omap3505()) {
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cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
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cpu_clkflg |= CK_3505;
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}
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}
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if (omap3_has_192mhz_clk())
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if (omap3_has_192mhz_clk())
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@ -284,8 +284,8 @@ static void __init omap3_check_revision(void)
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default:
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default:
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omap_revision = OMAP3630_REV_ES1_2;
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omap_revision = OMAP3630_REV_ES1_2;
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omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
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omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
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break;
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}
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}
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break;
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default:
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default:
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/* Unknown default to latest silicon rev as default*/
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/* Unknown default to latest silicon rev as default*/
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omap_revision = OMAP3630_REV_ES1_2;
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omap_revision = OMAP3630_REV_ES1_2;
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@ -177,7 +177,10 @@ omap_irq_base: .word 0
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cmpne \irqnr, \tmp
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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cmpcs \irqnr, \irqnr
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.endm
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.endm
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#endif
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#endif /* MULTI_OMAP2 */
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#ifdef CONFIG_SMP
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt
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* If there is an IPI, we immediately signal end of interrupt
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@ -205,8 +208,7 @@ omap_irq_base: .word 0
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streq \irqstat, [\base, #GIC_CPU_EOI]
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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cmp \tmp, #0
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.endm
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.endm
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#endif
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#endif /* CONFIG_SMP */
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#endif /* MULTI_OMAP2 */
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.macro irq_prio_table
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.macro irq_prio_table
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.endm
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.endm
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@ -102,8 +102,7 @@ static void __init wakeup_secondary(void)
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* Send a 'sev' to wake the secondary core from WFE.
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* Send a 'sev' to wake the secondary core from WFE.
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* Drain the outstanding writes to memory
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* Drain the outstanding writes to memory
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*/
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*/
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dsb();
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dsb_sev();
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set_event();
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mb();
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mb();
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}
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}
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@ -480,7 +480,9 @@ void omap_sram_idle(void)
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}
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}
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/* Disable IO-PAD and IO-CHAIN wakeup */
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/* Disable IO-PAD and IO-CHAIN wakeup */
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if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) {
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if (omap3_has_io_wakeup() &&
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(per_next_state < PWRDM_POWER_ON ||
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core_next_state < PWRDM_POWER_ON)) {
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prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
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prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
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omap3_disable_io_chain();
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omap3_disable_io_chain();
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}
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}
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@ -19,13 +19,6 @@
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#include <asm/hardware/gic.h>
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#include <asm/hardware/gic.h>
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/*
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* set_event() is used to wake up secondary core from wfe using sev. ROM
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* code puts the second core into wfe(standby).
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*
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*/
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#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
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/* Needed for secondary core boot */
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/* Needed for secondary core boot */
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extern void omap_secondary_startup(void);
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extern void omap_secondary_startup(void);
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extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
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extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
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