MLK-20052 L2 Cache TEE/Linux shared mutex
Modification of the L2 Cache operations to use a TEE/Linux Shared mutex Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>pull/10/head
Cedric Neveux
Silvano di Ninno
parent
0a1ce9e471
commit
a5b3a6a114
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@ -39,6 +39,11 @@ struct outer_cache_fns {
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/* This is an ARM L2C thing */
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void (*write_sec)(unsigned long, unsigned);
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void (*configure)(const struct l2x0_regs *);
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#ifdef CONFIG_OPTEE
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/* Set a mutex with OPTEE for maintenance */
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int (*set_mutex)(void *mutex);
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#endif
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};
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extern struct outer_cache_fns outer_cache;
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@ -115,6 +120,24 @@ static inline void outer_resume(void)
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outer_cache.resume();
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}
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#ifdef CONFIG_OPTEE
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/**
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* @brief Setup the Cache Mutex
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*
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* @param[in] Reference to the Mutex object
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*
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* @retval 0 Success
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* @retval -EINVAL Invalid value
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*/
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static inline int outer_mutex(void *mutex)
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{
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if (outer_cache.set_mutex)
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return outer_cache.set_mutex(mutex);
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return -EINVAL;
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}
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#endif
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#else
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static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
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@ -50,7 +50,6 @@ struct l2c_init_data {
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static void __iomem *l2x0_base;
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static const struct l2c_init_data *l2x0_data;
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static DEFINE_RAW_SPINLOCK(l2x0_lock);
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static u32 l2x0_way_mask; /* Bitmask of active ways */
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static u32 l2x0_size;
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static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
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@ -60,6 +59,90 @@ struct l2x0_regs l2x0_saved_regs;
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static bool l2x0_bresp_disable;
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static bool l2x0_flz_disable;
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#ifdef CONFIG_OPTEE
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struct l2x0_mutex {
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arch_rwlock_t *mutex;
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arch_rwlock_t nomutex;
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};
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static struct l2x0_mutex l2x0_lock;
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#define l2x0_spin_lock(lock, flags) \
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do { \
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flags = local_lock(lock); \
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} while (0)
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#define l2x0_spin_unlock(lock, flags) local_unlock(lock, flags)
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#define l2x0_spin_lock_init(lock) spinlock_init(lock)
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static void spinlock_init(struct l2x0_mutex *spinlock)
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{
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spinlock->mutex = NULL;
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spinlock->nomutex.lock = 0;
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}
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static unsigned long local_lock(struct l2x0_mutex *spinlock)
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{
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unsigned long flags;
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arch_rwlock_t *lock = spinlock->mutex;
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if (!lock)
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lock = &spinlock->nomutex;
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local_irq_save(flags);
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preempt_disable();
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arch_write_lock(lock);
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return flags;
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}
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static void local_unlock(struct l2x0_mutex *spinlock, unsigned long flags)
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{
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arch_rwlock_t *lock = spinlock->mutex;
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if (!lock)
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lock = &spinlock->nomutex;
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arch_write_unlock(lock);
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local_irq_restore(flags);
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preempt_enable();
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}
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static int l2c_set_mutex(void *mutex)
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{
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unsigned long flags;
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if (l2x0_lock.mutex != NULL)
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return -EINVAL;
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/* Ensure the no mutex is released */
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l2x0_spin_lock(&l2x0_lock, flags);
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l2x0_lock.mutex = mutex;
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arch_write_unlock(&l2x0_lock.nomutex);
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local_irq_restore(flags);
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preempt_enable();
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return 0;
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}
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#else
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static DEFINE_RAW_SPINLOCK(l2x0_lock);
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#define l2x0_spin_lock(lock, flags) raw_spin_lock_irqsave(lock, flags)
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#define l2x0_spin_unlock(lock, flags) raw_spin_unlock_irqrestore(lock, flags)
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#define l2x0_spin_lock_init(lock)
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static int l2c_set_mutex(void *mutex)
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{
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return -EINVAL;
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}
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#endif
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/*
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* Common code for all cache controllers.
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*/
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@ -287,17 +370,15 @@ static void l2c220_op_way(void __iomem *base, unsigned reg)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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__l2c_op_way(base + reg);
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__l2c220_cache_sync(base);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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}
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static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
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unsigned long end, unsigned long flags)
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{
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raw_spinlock_t *lock = &l2x0_lock;
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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@ -308,8 +389,8 @@ static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
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}
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if (blk_end < end) {
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raw_spin_unlock_irqrestore(lock, flags);
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raw_spin_lock_irqsave(lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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}
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}
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@ -321,7 +402,7 @@ static void l2c220_inv_range(unsigned long start, unsigned long end)
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void __iomem *base = l2x0_base;
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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if ((start | end) & (CACHE_LINE_SIZE - 1)) {
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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@ -340,7 +421,7 @@ static void l2c220_inv_range(unsigned long start, unsigned long end)
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start, end, flags);
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l2c_wait_mask(base + L2X0_INV_LINE_PA, 1);
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__l2c220_cache_sync(base);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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}
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static void l2c220_clean_range(unsigned long start, unsigned long end)
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@ -354,12 +435,12 @@ static void l2c220_clean_range(unsigned long start, unsigned long end)
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return;
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}
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA,
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start, end, flags);
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l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
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__l2c220_cache_sync(base);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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}
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static void l2c220_flush_range(unsigned long start, unsigned long end)
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@ -373,12 +454,12 @@ static void l2c220_flush_range(unsigned long start, unsigned long end)
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return;
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}
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA,
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start, end, flags);
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l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
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__l2c220_cache_sync(base);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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}
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static void l2c220_flush_all(void)
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@ -390,9 +471,9 @@ static void l2c220_sync(void)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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__l2c220_cache_sync(l2x0_base);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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}
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static void l2c220_enable(void __iomem *base, unsigned num_lock)
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@ -484,7 +565,7 @@ static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
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unsigned long flags;
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/* Erratum 588369 for both clean+invalidate operations */
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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l2c_set_debug(base, 0x03);
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if (start & (CACHE_LINE_SIZE - 1)) {
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@ -501,7 +582,7 @@ static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
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}
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l2c_set_debug(base, 0x00);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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}
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__l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
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@ -510,11 +591,10 @@ static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
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static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
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{
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raw_spinlock_t *lock = &l2x0_lock;
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unsigned long flags;
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void __iomem *base = l2x0_base;
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raw_spin_lock_irqsave(lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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@ -527,11 +607,11 @@ static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
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l2c_set_debug(base, 0x00);
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if (blk_end < end) {
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raw_spin_unlock_irqrestore(lock, flags);
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raw_spin_lock_irqsave(lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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}
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}
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raw_spin_unlock_irqrestore(lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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__l2c210_cache_sync(base);
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}
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@ -540,12 +620,12 @@ static void l2c310_flush_all_erratum(void)
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void __iomem *base = l2x0_base;
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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l2c_set_debug(base, 0x03);
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__l2c_op_way(base + L2X0_CLEAN_INV_WAY);
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l2c_set_debug(base, 0x00);
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__l2c210_cache_sync(base);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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}
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static void __init l2c310_save(void __iomem *base)
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@ -871,6 +951,10 @@ static int __init __l2c_init(const struct l2c_init_data *data,
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fns.sync = NULL;
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}
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#ifdef CONFIG_OPTEE
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fns.set_mutex = l2c_set_mutex;
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#endif
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/*
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* Check if l2x0 controller is already enabled. If we are booting
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* in non-secure mode accessing the below registers will fault.
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@ -1400,10 +1484,10 @@ static void aurora_pa_range(unsigned long start, unsigned long end,
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while (start < end) {
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range_end = aurora_range_end(start, end);
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG);
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writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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writel_relaxed(0, base + AURORA_SYNC_REG);
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start = range_end;
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@ -1438,9 +1522,9 @@ static void aurora_flush_all(void)
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unsigned long flags;
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/* clean all ways */
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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__l2c_op_way(base + L2X0_CLEAN_INV_WAY);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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writel_relaxed(0, base + AURORA_SYNC_REG);
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}
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@ -1455,12 +1539,12 @@ static void aurora_disable(void)
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void __iomem *base = l2x0_base;
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unsigned long flags;
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raw_spin_lock_irqsave(&l2x0_lock, flags);
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l2x0_spin_lock(&l2x0_lock, flags);
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__l2c_op_way(base + L2X0_CLEAN_INV_WAY);
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writel_relaxed(0, base + AURORA_SYNC_REG);
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l2c_write_sec(0, base, L2X0_CTRL);
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dsb(st);
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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l2x0_spin_unlock(&l2x0_lock, flags);
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}
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static void aurora_save(void __iomem *base)
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@ -1817,6 +1901,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
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else
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cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
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l2x0_spin_lock_init(&l2x0_lock);
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return __l2c_init(data, aux_val, aux_mask, cache_id, nosync);
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}
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#endif
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@ -29,6 +29,10 @@
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#include "optee_private.h"
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#include "optee_smc.h"
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#ifdef CONFIG_OUTER_CACHE
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#include <asm/outercache.h>
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#endif
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#define DRIVER_NAME "optee"
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#define OPTEE_SHM_NUM_PRIV_PAGES 1
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@ -404,6 +408,70 @@ out:
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return pool;
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}
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#ifdef CONFIG_OUTER_CACHE
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/**
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* @brief Call the TEE to get a shared mutex between TEE and Linux to
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* do Outer Cache maintenance
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*
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* @param[in] invoke_fn Reference to the SMC call function
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*
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* @retval 0 Success
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* @retval -EINVAL Invalid value
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* @retval -ENOMEM Not enought memory
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*/
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static int optee_outercache_mutex(optee_invoke_fn *invoke_fn)
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{
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struct arm_smccc_res res;
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int ret = -EINVAL;
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void *vaddr = NULL;
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phys_addr_t paddr = 0;
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/* Get the Physical Address of the mutex allocated in the SHM */
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invoke_fn(OPTEE_SMC_L2CC_MUTEX,
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OPTEE_SMC_L2CC_MUTEX_GET_ADDR, 0, 0, 0, 0, 0, 0, &res);
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if (res.a0 != OPTEE_SMC_RETURN_OK) {
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pr_warn("no TZ l2cc mutex service supported\n");
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goto out;
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}
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paddr = (unsigned long)reg_pair_to_ptr(res.a2, res.a3);
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pr_debug("outer cache shared mutex paddr 0x%lx\n", (unsigned long)paddr);
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/* Remap the Mutex into a cacheable area */
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vaddr = memremap(paddr, sizeof(u32), MEMREMAP_WB);
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if (vaddr == NULL) {
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pr_warn("TZ l2cc mutex: ioremap failed\n");
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ret = -ENOMEM;
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goto out;
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}
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pr_debug("outer cache shared mutex vaddr %p\n", vaddr);
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if (outer_mutex(vaddr)) {
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pr_warn("TZ l2cc mutex: outer cache refused\n");
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goto out;
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}
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invoke_fn(OPTEE_SMC_L2CC_MUTEX,
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OPTEE_SMC_L2CC_MUTEX_ENABLE, 0, 0, 0, 0, 0, 0, &res);
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if (res.a0 != OPTEE_SMC_RETURN_OK) {
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pr_warn("TZ l2cc mutex disabled: TZ enable failed\n");
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goto out;
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}
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ret = 0;
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out:
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pr_info("teetz outer mutex: ret=%d pa=0x%lx va=0x%p\n",
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ret, (unsigned long)paddr, vaddr);
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return ret;
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}
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#endif
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/* Simple wrapper functions to be able to use a function pointer */
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static void optee_smccc_smc(unsigned long a0, unsigned long a1,
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unsigned long a2, unsigned long a3,
|
||||
|
|
@ -483,6 +551,17 @@ static struct optee *optee_probe(struct device_node *np)
|
|||
if (IS_ERR(pool))
|
||||
return (void *)pool;
|
||||
|
||||
#ifdef CONFIG_OUTER_CACHE
|
||||
|
||||
/* Try to get a Share Mutex to do L2 Cache maintenance */
|
||||
if (of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
|
||||
rc = optee_outercache_mutex(invoke_fn);
|
||||
if (rc)
|
||||
goto err;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
optee = kzalloc(sizeof(*optee), GFP_KERNEL);
|
||||
if (!optee) {
|
||||
rc = -ENOMEM;
|
||||
|
|
|
|||
|
|
@ -197,6 +197,49 @@ struct optee_smc_get_shm_config_result {
|
|||
unsigned long settings;
|
||||
};
|
||||
|
||||
/*
|
||||
* Configures L2CC mutex
|
||||
*
|
||||
* Disables, enables usage of L2CC mutex. Returns or sets physical address
|
||||
* of L2CC mutex.
|
||||
*
|
||||
* Call register usage:
|
||||
* a0 SMC Function ID, OPTEE_SMC_L2CC_MUTEX
|
||||
* a1 OPTEE_SMC_L2CC_MUTEX_GET_ADDR Get physical address of mutex
|
||||
* OPTEE_SMC_L2CC_MUTEX_SET_ADDR Set physical address of mutex
|
||||
* OPTEE_SMC_L2CC_MUTEX_ENABLE Enable usage of mutex
|
||||
* OPTEE_SMC_L2CC_MUTEX_DISABLE Disable usage of mutex
|
||||
* a2 if a1 == OPTEE_SMC_L2CC_MUTEX_SET_ADDR, upper 32bit of a 64bit
|
||||
* physical address of mutex
|
||||
* a3 if a1 == OPTEE_SMC_L2CC_MUTEX_SET_ADDR, lower 32bit of a 64bit
|
||||
* physical address of mutex
|
||||
* a3-6 Not used
|
||||
* a7 Hypervisor Client ID register
|
||||
*
|
||||
* Have config return register usage:
|
||||
* a0 OPTEE_SMC_RETURN_OK
|
||||
* a1 Preserved
|
||||
* a2 if a1 == OPTEE_SMC_L2CC_MUTEX_GET_ADDR, upper 32bit of a 64bit
|
||||
* physical address of mutex
|
||||
* a3 if a1 == OPTEE_SMC_L2CC_MUTEX_GET_ADDR, lower 32bit of a 64bit
|
||||
* physical address of mutex
|
||||
* a3-7 Preserved
|
||||
*
|
||||
* Error return register usage:
|
||||
* a0 OPTEE_SMC_RETURN_ENOTAVAIL Physical address not available
|
||||
* OPTEE_SMC_RETURN_EBADADDR Bad supplied physical address
|
||||
* OPTEE_SMC_RETURN_EBADCMD Unsupported value in a1
|
||||
* a1-7 Preserved
|
||||
*/
|
||||
#define OPTEE_SMC_L2CC_MUTEX_GET_ADDR 0
|
||||
#define OPTEE_SMC_L2CC_MUTEX_SET_ADDR 1
|
||||
#define OPTEE_SMC_L2CC_MUTEX_ENABLE 2
|
||||
#define OPTEE_SMC_L2CC_MUTEX_DISABLE 3
|
||||
|
||||
#define OPTEE_SMC_FUNCID_L2CC_MUTEX 8
|
||||
#define OPTEE_SMC_L2CC_MUTEX \
|
||||
OPTEE_SMC_FAST_CALL_VAL(OPTEE_SMC_FUNCID_L2CC_MUTEX)
|
||||
|
||||
/*
|
||||
* Exchanges capabilities between normal world and secure world
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue