arch/tile: sync up with <arch/sim.h> and <arch/sim_def.h> changes
These headers are used by Linux but are maintained upstream. This change incorporates a few minor fixes to these headers, including a new sim_print() function, cleaner support for the sim_syscall() API, and a sim_query_cpu_speed() method. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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@ -152,16 +152,33 @@ sim_dump(unsigned int mask)
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/**
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/**
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* Print a string to the simulator stdout.
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* Print a string to the simulator stdout.
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*
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*
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* @param str The string to be written; a newline is automatically added.
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* @param str The string to be written.
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*/
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static __inline void
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sim_print(const char* str)
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{
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for ( ; *str != '\0'; str++)
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{
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
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(*str << _SIM_CONTROL_OPERATOR_BITS));
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}
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
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(SIM_PUTC_FLUSH_BINARY << _SIM_CONTROL_OPERATOR_BITS));
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}
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/**
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* Print a string to the simulator stdout.
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*
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* @param str The string to be written (a newline is automatically added).
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*/
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*/
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static __inline void
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static __inline void
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sim_print_string(const char* str)
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sim_print_string(const char* str)
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{
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{
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int i;
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for ( ; *str != '\0'; str++)
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for (i = 0; str[i] != 0; i++)
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{
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{
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
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(str[i] << _SIM_CONTROL_OPERATOR_BITS));
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(*str << _SIM_CONTROL_OPERATOR_BITS));
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}
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}
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
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(SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS));
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(SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS));
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@ -203,7 +220,7 @@ sim_command(const char* str)
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* we are passing to the simulator are actually valid in the registers
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* we are passing to the simulator are actually valid in the registers
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* (i.e. returned from memory) prior to the SIM_CONTROL spr.
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* (i.e. returned from memory) prior to the SIM_CONTROL spr.
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*/
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*/
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static __inline int _sim_syscall0(int val)
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static __inline long _sim_syscall0(int val)
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{
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{
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long result;
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long result;
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__asm__ __volatile__ ("mtspr SIM_CONTROL, r0"
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__asm__ __volatile__ ("mtspr SIM_CONTROL, r0"
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@ -211,7 +228,7 @@ static __inline int _sim_syscall0(int val)
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return result;
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return result;
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}
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}
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static __inline int _sim_syscall1(int val, long arg1)
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static __inline long _sim_syscall1(int val, long arg1)
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{
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{
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long result;
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long result;
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__asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
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__asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
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@ -219,7 +236,7 @@ static __inline int _sim_syscall1(int val, long arg1)
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return result;
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return result;
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}
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}
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static __inline int _sim_syscall2(int val, long arg1, long arg2)
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static __inline long _sim_syscall2(int val, long arg1, long arg2)
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{
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{
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long result;
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long result;
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__asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
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__asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
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@ -233,7 +250,7 @@ static __inline int _sim_syscall2(int val, long arg1, long arg2)
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the register values for arguments 3 and up may still be in flight
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the register values for arguments 3 and up may still be in flight
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to the core from a stack frame reload. */
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to the core from a stack frame reload. */
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static __inline int _sim_syscall3(int val, long arg1, long arg2, long arg3)
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static __inline long _sim_syscall3(int val, long arg1, long arg2, long arg3)
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{
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{
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long result;
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long result;
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__asm__ __volatile__ ("{ and zero, r3, r3 };"
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__asm__ __volatile__ ("{ and zero, r3, r3 };"
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@ -244,7 +261,7 @@ static __inline int _sim_syscall3(int val, long arg1, long arg2, long arg3)
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return result;
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return result;
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}
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}
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static __inline int _sim_syscall4(int val, long arg1, long arg2, long arg3,
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static __inline long _sim_syscall4(int val, long arg1, long arg2, long arg3,
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long arg4)
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long arg4)
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{
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{
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long result;
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long result;
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@ -256,7 +273,7 @@ static __inline int _sim_syscall4(int val, long arg1, long arg2, long arg3,
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return result;
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return result;
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}
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}
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static __inline int _sim_syscall5(int val, long arg1, long arg2, long arg3,
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static __inline long _sim_syscall5(int val, long arg1, long arg2, long arg3,
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long arg4, long arg5)
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long arg4, long arg5)
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{
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{
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long result;
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long result;
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@ -268,7 +285,6 @@ static __inline int _sim_syscall5(int val, long arg1, long arg2, long arg3,
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return result;
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return result;
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}
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}
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/**
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/**
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* Make a special syscall to the simulator itself, if running under
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* Make a special syscall to the simulator itself, if running under
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* simulation. This is used as the implementation of other functions
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* simulation. This is used as the implementation of other functions
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@ -281,7 +297,8 @@ static __inline int _sim_syscall5(int val, long arg1, long arg2, long arg3,
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*/
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*/
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#define _sim_syscall(syscall_num, nr, args...) \
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#define _sim_syscall(syscall_num, nr, args...) \
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_sim_syscall##nr( \
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_sim_syscall##nr( \
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((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, args)
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((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, \
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##args)
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/* Values for the "access_mask" parameters below. */
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/* Values for the "access_mask" parameters below. */
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@ -365,6 +382,13 @@ sim_validate_lines_evicted(unsigned long long pa, unsigned long length)
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}
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}
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/* Return the current CPU speed in cycles per second. */
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static __inline long
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sim_query_cpu_speed(void)
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{
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return _sim_syscall(SIM_SYSCALL_QUERY_CPU_SPEED, 0);
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}
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#endif /* !__DOXYGEN__ */
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#endif /* !__DOXYGEN__ */
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@ -243,6 +243,9 @@
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*/
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*/
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#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
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#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
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/** Syscall number for sim_query_cpu_speed(). */
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#define SIM_SYSCALL_QUERY_CPU_SPEED 6
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/*
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/*
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* Bit masks which can be shifted by 8, combined with
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* Bit masks which can be shifted by 8, combined with
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