ARM: EXYNOS: Add bus clock for FIMD
This patch adds the bus clock for FIMD and changes the device name for lcd clock Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -891,6 +891,13 @@ static struct clk exynos5_clk_mdma1 = {
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.ctrlbit = (1 << 4),
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};
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static struct clk exynos5_clk_fimd1 = {
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.name = "fimd",
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.devname = "exynos5-fb.1",
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.enable = exynos5_clk_ip_disp1_ctrl,
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.ctrlbit = (1 << 0),
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};
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struct clk *exynos5_clkset_group_list[] = {
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[0] = &clk_ext_xtal_mux,
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[1] = NULL,
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@ -1120,6 +1127,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
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.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
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};
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struct clksrc_clk exynos5_clk_sclk_fimd1 = {
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.clk = {
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.name = "sclk_fimd",
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.devname = "exynos5-fb.1",
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.enable = exynos5_clksrc_mask_disp1_0_ctrl,
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.ctrlbit = (1 << 0),
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},
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.sources = &exynos5_clkset_group,
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.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
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.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk exynos5_clksrcs[] = {
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{
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.clk = {
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@ -1129,16 +1148,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
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.ctrlbit = (1 << 16),
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},
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.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
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}, {
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.clk = {
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.name = "sclk_fimd",
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.devname = "s3cfb.1",
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.enable = exynos5_clksrc_mask_disp1_0_ctrl,
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.ctrlbit = (1 << 0),
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},
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.sources = &exynos5_clkset_group,
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.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
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.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "aclk_266_gscl",
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@ -1240,12 +1249,14 @@ static struct clksrc_clk *exynos5_sysclks[] = {
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&exynos5_clk_mdout_spi0,
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&exynos5_clk_mdout_spi1,
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&exynos5_clk_mdout_spi2,
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&exynos5_clk_sclk_fimd1,
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};
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static struct clk *exynos5_clk_cdev[] = {
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&exynos5_clk_pdma0,
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&exynos5_clk_pdma1,
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&exynos5_clk_mdma1,
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&exynos5_clk_fimd1,
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};
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static struct clksrc_clk *exynos5_clksrc_cdev[] = {
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@ -1274,6 +1285,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
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CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
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CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
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CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
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CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
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};
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static unsigned long exynos5_epll_get_rate(struct clk *clk)
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