[ARM] pxa: introduce clk support for PXA SoC clocks
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
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00dc4f949e
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a6dba20c5c
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@ -9,19 +9,15 @@
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/hardware.h>
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struct clk {
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struct list_head node;
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unsigned long rate;
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struct module *owner;
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const char *name;
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unsigned int enabled;
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void (*enable)(void);
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void (*disable)(void);
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};
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#include "devices.h"
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#include "generic.h"
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#include "clock.h"
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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@ -33,7 +29,8 @@ struct clk *clk_get(struct device *dev, const char *id)
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mutex_lock(&clocks_mutex);
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list_for_each_entry(p, &clocks, node) {
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if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
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if (strcmp(id, p->name) == 0 &&
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(p->dev == NULL || p->dev == dev)) {
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clk = p;
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break;
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}
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@ -46,7 +43,6 @@ EXPORT_SYMBOL(clk_get);
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void clk_put(struct clk *clk)
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{
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module_put(clk->owner);
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}
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EXPORT_SYMBOL(clk_put);
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@ -56,8 +52,12 @@ int clk_enable(struct clk *clk)
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spin_lock_irqsave(&clocks_lock, flags);
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if (clk->enabled++ == 0)
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clk->enable();
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clk->ops->enable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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if (clk->delay)
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udelay(clk->delay);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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@ -70,54 +70,75 @@ void clk_disable(struct clk *clk)
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spin_lock_irqsave(&clocks_lock, flags);
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if (--clk->enabled == 0)
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clk->disable();
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clk->ops->disable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return clk->rate;
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unsigned long rate;
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rate = clk->rate;
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if (clk->ops->getrate)
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rate = clk->ops->getrate(clk);
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return rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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static void clk_gpio27_enable(void)
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static void clk_gpio27_enable(struct clk *clk)
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{
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pxa_gpio_mode(GPIO11_3_6MHz_MD);
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}
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static void clk_gpio27_disable(void)
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static void clk_gpio27_disable(struct clk *clk)
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{
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}
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static struct clk clk_gpio27 = {
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.name = "GPIO27_CLK",
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.rate = 3686400,
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static const struct clkops clk_gpio27_ops = {
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.enable = clk_gpio27_enable,
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.disable = clk_gpio27_disable,
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};
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int clk_register(struct clk *clk)
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{
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mutex_lock(&clocks_mutex);
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list_add(&clk->node, &clocks);
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mutex_unlock(&clocks_mutex);
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return 0;
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}
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EXPORT_SYMBOL(clk_register);
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void clk_unregister(struct clk *clk)
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void clk_cken_enable(struct clk *clk)
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{
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CKEN |= 1 << clk->cken;
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}
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void clk_cken_disable(struct clk *clk)
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{
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CKEN &= ~(1 << clk->cken);
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}
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const struct clkops clk_cken_ops = {
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.enable = clk_cken_enable,
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.disable = clk_cken_disable,
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};
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static struct clk common_clks[] = {
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{
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.name = "GPIO27_CLK",
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.ops = &clk_gpio27_ops,
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.rate = 3686400,
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},
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};
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void clks_register(struct clk *clks, size_t num)
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{
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int i;
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mutex_lock(&clocks_mutex);
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list_del(&clk->node);
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for (i = 0; i < num; i++)
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list_add(&clks[i].node, &clocks);
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mutex_unlock(&clocks_mutex);
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}
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EXPORT_SYMBOL(clk_unregister);
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static int __init clk_init(void)
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{
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clk_register(&clk_gpio27);
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clks_register(common_clks, ARRAY_SIZE(common_clks));
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return 0;
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}
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arch_initcall(clk_init);
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43
arch/arm/mach-pxa/clock.h
Normal file
43
arch/arm/mach-pxa/clock.h
Normal file
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@ -0,0 +1,43 @@
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struct clk;
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struct clkops {
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void (*enable)(struct clk *);
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void (*disable)(struct clk *);
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unsigned long (*getrate)(struct clk *);
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};
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struct clk {
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struct list_head node;
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const char *name;
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struct device *dev;
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const struct clkops *ops;
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unsigned long rate;
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unsigned int cken;
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unsigned int delay;
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unsigned int enabled;
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};
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#define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \
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{ \
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.name = _name, \
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.dev = _dev, \
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.ops = &clk_cken_ops, \
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.rate = _rate, \
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.cken = CKEN_##_cken, \
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.delay = _delay, \
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}
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#define INIT_CK(_name, _cken, _ops, _dev) \
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{ \
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.name = _name, \
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.dev = _dev, \
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.ops = _ops, \
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.cken = CKEN_##_cken, \
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}
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extern const struct clkops clk_cken_ops;
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void clk_cken_enable(struct clk *clk);
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void clk_cken_disable(struct clk *clk);
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void clks_register(struct clk *clks, size_t num);
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@ -30,6 +30,7 @@
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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/*
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* Various clock factors driven by the CCCR register.
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@ -94,6 +95,41 @@ unsigned int pxa25x_get_memclk_frequency_10khz(void)
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return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
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}
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static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
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{
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return pxa25x_get_memclk_frequency_10khz() * 10000;
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}
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static const struct clkops clk_pxa25x_lcd_ops = {
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.enable = clk_cken_enable,
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.disable = clk_cken_disable,
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.getrate = clk_pxa25x_lcd_getrate,
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};
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/*
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* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
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* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
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* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
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*/
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static struct clk pxa25x_clks[] = {
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INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
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INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
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INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
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INIT_CKEN("UARTCLK", STUART, 14745600, 1, &pxa_device_stuart.dev),
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INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
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INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
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INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
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INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
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/*
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INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
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INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
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INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL),
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INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
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INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL),
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INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
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*/
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};
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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@ -215,6 +251,8 @@ static int __init pxa25x_init(void)
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int ret = 0;
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if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
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clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
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if ((ret = pxa_init_dma(16)))
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return ret;
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#ifdef CONFIG_PM
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@ -27,6 +27,7 @@
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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@ -120,6 +121,48 @@ unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
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return (K / 10000);
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}
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static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
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{
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return pxa27x_get_lcdclk_frequency_10khz() * 10000;
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}
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static const struct clkops clk_pxa27x_lcd_ops = {
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.enable = clk_cken_enable,
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.disable = clk_cken_disable,
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.getrate = clk_pxa27x_lcd_getrate,
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};
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static struct clk pxa27x_clks[] = {
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INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
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INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
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INIT_CKEN("UARTCLK", STUART, 14857000, 1, &pxa_device_stuart.dev),
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INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
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INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
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INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev),
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INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
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INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev),
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INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev),
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INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
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INIT_CKEN("USBCLK", USB, 48000000, 0, &pxa27x_device_ohci.dev),
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INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
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INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
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/*
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INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
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INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL),
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INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL),
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INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL),
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INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
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INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
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INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
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INIT_CKEN("IMCLK", IM, 0, 0, NULL),
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INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL),
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*/
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};
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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@ -343,6 +386,8 @@ static int __init pxa27x_init(void)
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{
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int ret = 0;
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if (cpu_is_pxa27x()) {
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clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
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if ((ret = pxa_init_dma(32)))
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return ret;
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#ifdef CONFIG_PM
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