drm/nouveau/instmem/gk20a: move memory allocation to instmem
GK20A does not have dedicated RAM, thus having a RAM device for it does not make sense. Move the contiguous physical memory allocation to instmem. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot
Ben Skeggs
parent
eaecf0326f
commit
a6ff85d386
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@ -45,4 +45,5 @@ nvkm_instmem(void *obj)
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extern struct nvkm_oclass *nv04_instmem_oclass;
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extern struct nvkm_oclass *nv40_instmem_oclass;
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extern struct nvkm_oclass *nv50_instmem_oclass;
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extern struct nvkm_oclass *gk20a_instmem_oclass;
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#endif
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@ -171,7 +171,7 @@ gk104_identify(struct nvkm_device *device)
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device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
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@ -23,99 +23,17 @@
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#include <core/device.h>
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struct gk20a_mem {
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struct nvkm_mem base;
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void *cpuaddr;
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dma_addr_t handle;
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};
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#define to_gk20a_mem(m) container_of(m, struct gk20a_mem, base)
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static void
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gk20a_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem)
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{
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struct device *dev = nv_device_base(nv_device(pfb));
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struct gk20a_mem *mem = to_gk20a_mem(*pmem);
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*pmem = NULL;
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if (unlikely(mem == NULL))
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return;
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if (likely(mem->cpuaddr))
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dma_free_coherent(dev, mem->base.size << PAGE_SHIFT,
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mem->cpuaddr, mem->handle);
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kfree(mem->base.pages);
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kfree(mem);
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BUG();
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}
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static int
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gk20a_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin,
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u32 memtype, struct nvkm_mem **pmem)
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{
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struct device *dev = nv_device_base(nv_device(pfb));
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struct gk20a_mem *mem;
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u32 type = memtype & 0xff;
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u32 npages, order;
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int i;
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nv_debug(pfb, "%s: size: %llx align: %x, ncmin: %x\n", __func__, size,
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align, ncmin);
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npages = size >> PAGE_SHIFT;
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if (npages == 0)
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npages = 1;
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if (align == 0)
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align = PAGE_SIZE;
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align >>= PAGE_SHIFT;
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/* round alignment to the next power of 2, if needed */
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order = fls(align);
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if ((align & (align - 1)) == 0)
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order--;
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align = BIT(order);
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/* ensure returned address is correctly aligned */
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npages = max(align, npages);
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mem = kzalloc(sizeof(*mem), GFP_KERNEL);
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if (!mem)
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return -ENOMEM;
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mem->base.size = npages;
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mem->base.memtype = type;
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mem->base.pages = kzalloc(sizeof(dma_addr_t) * npages, GFP_KERNEL);
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if (!mem->base.pages) {
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kfree(mem);
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return -ENOMEM;
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}
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*pmem = &mem->base;
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mem->cpuaddr = dma_alloc_coherent(dev, npages << PAGE_SHIFT,
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&mem->handle, GFP_KERNEL);
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if (!mem->cpuaddr) {
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nv_error(pfb, "%s: cannot allocate memory!\n", __func__);
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gk20a_ram_put(pfb, pmem);
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return -ENOMEM;
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}
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align <<= PAGE_SHIFT;
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/* alignment check */
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if (unlikely(mem->handle & (align - 1)))
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nv_warn(pfb, "memory not aligned as requested: %pad (0x%x)\n",
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&mem->handle, align);
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nv_debug(pfb, "alloc size: 0x%x, align: 0x%x, paddr: %pad, vaddr: %p\n",
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npages << PAGE_SHIFT, align, &mem->handle, mem->cpuaddr);
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for (i = 0; i < npages; i++)
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mem->base.pages[i] = mem->handle + (PAGE_SIZE * i);
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mem->base.offset = (u64)mem->base.pages[0];
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return 0;
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BUG();
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}
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static int
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@ -2,3 +2,4 @@ nvkm-y += nvkm/subdev/instmem/base.o
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nvkm-y += nvkm/subdev/instmem/nv04.o
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nvkm-y += nvkm/subdev/instmem/nv40.o
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nvkm-y += nvkm/subdev/instmem/nv50.o
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nvkm-y += nvkm/subdev/instmem/gk20a.o
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211
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
Normal file
211
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
Normal file
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@ -0,0 +1,211 @@
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/*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <subdev/fb.h>
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#include <core/mm.h>
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#include <core/device.h>
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#include "priv.h"
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struct gk20a_instobj_priv {
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struct nvkm_instobj base;
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/* Must be second member here - see nouveau_gpuobj_map_vm() */
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struct nvkm_mem *mem;
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/* Pointed by mem */
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struct nvkm_mem _mem;
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void *cpuaddr;
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dma_addr_t handle;
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struct nvkm_mm_node r;
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};
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struct gk20a_instmem_priv {
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struct nvkm_instmem base;
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spinlock_t lock;
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u64 addr;
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};
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static u32
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gk20a_instobj_rd32(struct nvkm_object *object, u64 offset)
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{
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struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(object);
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struct gk20a_instobj_priv *node = (void *)object;
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unsigned long flags;
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u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
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u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
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u32 data;
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spin_lock_irqsave(&priv->lock, flags);
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if (unlikely(priv->addr != base)) {
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nv_wr32(priv, 0x001700, base >> 16);
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priv->addr = base;
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}
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data = nv_rd32(priv, 0x700000 + addr);
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spin_unlock_irqrestore(&priv->lock, flags);
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return data;
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}
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static void
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gk20a_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data)
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{
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struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(object);
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struct gk20a_instobj_priv *node = (void *)object;
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unsigned long flags;
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u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
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u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
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spin_lock_irqsave(&priv->lock, flags);
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if (unlikely(priv->addr != base)) {
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nv_wr32(priv, 0x001700, base >> 16);
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priv->addr = base;
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}
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nv_wr32(priv, 0x700000 + addr, data);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void
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gk20a_instobj_dtor(struct nvkm_object *object)
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{
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struct gk20a_instobj_priv *node = (void *)object;
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struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(node);
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struct device *dev = nv_device_base(nv_device(priv));
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if (unlikely(!node->handle))
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return;
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dma_free_coherent(dev, node->mem->size << PAGE_SHIFT, node->cpuaddr,
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node->handle);
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nvkm_instobj_destroy(&node->base);
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}
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static int
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gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 _size,
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struct nvkm_object **pobject)
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{
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struct nvkm_instobj_args *args = data;
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struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(parent);
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struct device *dev = nv_device_base(nv_device(priv));
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struct gk20a_instobj_priv *node;
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u32 size, align;
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u32 npages;
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int ret;
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nv_debug(parent, "%s: size: %x align: %x\n", __func__,
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args->size, args->align);
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size = max((args->size + 4095) & ~4095, (u32)4096);
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align = max((args->align + 4095) & ~4095, (u32)4096);
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npages = size >> PAGE_SHIFT;
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ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node),
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(void **)&node);
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*pobject = nv_object(node);
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if (ret)
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return ret;
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node->mem = &node->_mem;
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node->cpuaddr = dma_alloc_coherent(dev, npages << PAGE_SHIFT,
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&node->handle, GFP_KERNEL);
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if (!node->cpuaddr) {
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nv_error(priv, "cannot allocate DMA memory\n");
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return -ENOMEM;
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}
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/* alignment check */
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if (unlikely(node->handle & (align - 1)))
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nv_warn(priv, "memory not aligned as requested: %pad (0x%x)\n",
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&node->handle, align);
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node->mem->offset = node->handle;
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node->mem->size = size >> 12;
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node->mem->memtype = 0;
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node->mem->page_shift = 12;
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INIT_LIST_HEAD(&node->mem->regions);
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node->r.type = 12;
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node->r.offset = node->handle >> 12;
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node->r.length = npages;
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list_add_tail(&node->r.rl_entry, &node->mem->regions);
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node->base.addr = node->mem->offset;
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node->base.size = size;
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nv_debug(parent, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
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size, align, node->mem->offset);
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return 0;
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}
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static struct nvkm_instobj_impl
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gk20a_instobj_oclass = {
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = gk20a_instobj_ctor,
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.dtor = gk20a_instobj_dtor,
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.init = _nvkm_instobj_init,
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.fini = _nvkm_instobj_fini,
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.rd32 = gk20a_instobj_rd32,
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.wr32 = gk20a_instobj_wr32,
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},
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};
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static int
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gk20a_instmem_fini(struct nvkm_object *object, bool suspend)
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{
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struct gk20a_instmem_priv *priv = (void *)object;
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priv->addr = ~0ULL;
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return nvkm_instmem_fini(&priv->base, suspend);
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}
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static int
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gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct gk20a_instmem_priv *priv;
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int ret;
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ret = nvkm_instmem_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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spin_lock_init(&priv->lock);
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return 0;
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}
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struct nvkm_oclass *
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gk20a_instmem_oclass = &(struct nvkm_instmem_impl) {
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.base.handle = NV_SUBDEV(INSTMEM, 0xea),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = gk20a_instmem_ctor,
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.dtor = _nvkm_instmem_dtor,
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.init = _nvkm_instmem_init,
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.fini = gk20a_instmem_fini,
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},
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.instobj = &gk20a_instobj_oclass.base,
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}.base;
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