[TG3]: Add register test
Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>wifi-calibration
Michael Chan
David S. Miller
parent
944d980eca
commit
a71116d1f3
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@ -7307,6 +7307,219 @@ static int tg3_test_link(struct tg3 *tp)
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return -EIO;
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}
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/* Only test the commonly used registers */
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static int tg3_test_registers(struct tg3 *tp)
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{
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int i, is_5705;
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u32 offset, read_mask, write_mask, val, save_val, read_val;
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static struct {
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u16 offset;
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u16 flags;
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#define TG3_FL_5705 0x1
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#define TG3_FL_NOT_5705 0x2
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#define TG3_FL_NOT_5788 0x4
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u32 read_mask;
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u32 write_mask;
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} reg_tbl[] = {
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/* MAC Control Registers */
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{ MAC_MODE, TG3_FL_NOT_5705,
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0x00000000, 0x00ef6f8c },
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{ MAC_MODE, TG3_FL_5705,
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0x00000000, 0x01ef6b8c },
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{ MAC_STATUS, TG3_FL_NOT_5705,
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0x03800107, 0x00000000 },
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{ MAC_STATUS, TG3_FL_5705,
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0x03800100, 0x00000000 },
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{ MAC_ADDR_0_HIGH, 0x0000,
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0x00000000, 0x0000ffff },
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{ MAC_ADDR_0_LOW, 0x0000,
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0x00000000, 0xffffffff },
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{ MAC_RX_MTU_SIZE, 0x0000,
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0x00000000, 0x0000ffff },
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{ MAC_TX_MODE, 0x0000,
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0x00000000, 0x00000070 },
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{ MAC_TX_LENGTHS, 0x0000,
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0x00000000, 0x00003fff },
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{ MAC_RX_MODE, TG3_FL_NOT_5705,
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0x00000000, 0x000007fc },
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{ MAC_RX_MODE, TG3_FL_5705,
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0x00000000, 0x000007dc },
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{ MAC_HASH_REG_0, 0x0000,
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0x00000000, 0xffffffff },
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{ MAC_HASH_REG_1, 0x0000,
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0x00000000, 0xffffffff },
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{ MAC_HASH_REG_2, 0x0000,
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0x00000000, 0xffffffff },
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{ MAC_HASH_REG_3, 0x0000,
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0x00000000, 0xffffffff },
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/* Receive Data and Receive BD Initiator Control Registers. */
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{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
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0x00000000, 0x00000003 },
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{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ RCVDBDI_STD_BD+0, 0x0000,
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0x00000000, 0xffffffff },
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{ RCVDBDI_STD_BD+4, 0x0000,
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0x00000000, 0xffffffff },
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{ RCVDBDI_STD_BD+8, 0x0000,
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0x00000000, 0xffff0002 },
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{ RCVDBDI_STD_BD+0xc, 0x0000,
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0x00000000, 0xffffffff },
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/* Receive BD Initiator Control Registers. */
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{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ RCVBDI_STD_THRESH, TG3_FL_5705,
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0x00000000, 0x000003ff },
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{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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/* Host Coalescing Control Registers. */
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{ HOSTCC_MODE, TG3_FL_NOT_5705,
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0x00000000, 0x00000004 },
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{ HOSTCC_MODE, TG3_FL_5705,
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0x00000000, 0x000000f6 },
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{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_RXCOL_TICKS, TG3_FL_5705,
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0x00000000, 0x000003ff },
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{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_TXCOL_TICKS, TG3_FL_5705,
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0x00000000, 0x000003ff },
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{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
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0x00000000, 0x000000ff },
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{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
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0x00000000, 0x000000ff },
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{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
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0x00000000, 0x000000ff },
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{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
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0x00000000, 0x000000ff },
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{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
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0x00000000, 0xffffffff },
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{ HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
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0x00000000, 0xffffffff },
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{ HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
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0x00000000, 0xffffffff },
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{ HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
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0xffffffff, 0x00000000 },
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{ HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
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0xffffffff, 0x00000000 },
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/* Buffer Manager Control Registers. */
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{ BUFMGR_MB_POOL_ADDR, 0x0000,
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0x00000000, 0x007fff80 },
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{ BUFMGR_MB_POOL_SIZE, 0x0000,
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0x00000000, 0x007fffff },
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{ BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
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0x00000000, 0x0000003f },
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{ BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
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0x00000000, 0x000001ff },
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{ BUFMGR_MB_HIGH_WATER, 0x0000,
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0x00000000, 0x000001ff },
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{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
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0xffffffff, 0x00000000 },
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{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
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0xffffffff, 0x00000000 },
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/* Mailbox Registers */
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{ GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
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0x00000000, 0x000001ff },
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{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
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0x00000000, 0x000001ff },
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{ GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
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0x00000000, 0x000007ff },
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{ GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
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0x00000000, 0x000001ff },
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{ 0xffff, 0x0000, 0x00000000, 0x00000000 },
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};
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
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is_5705 = 1;
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else
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is_5705 = 0;
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for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
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if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
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continue;
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if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
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continue;
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if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
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(reg_tbl[i].flags & TG3_FL_NOT_5788))
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continue;
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offset = (u32) reg_tbl[i].offset;
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read_mask = reg_tbl[i].read_mask;
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write_mask = reg_tbl[i].write_mask;
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/* Save the original register content */
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save_val = tr32(offset);
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/* Determine the read-only value. */
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read_val = save_val & read_mask;
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/* Write zero to the register, then make sure the read-only bits
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* are not changed and the read/write bits are all zeros.
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*/
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tw32(offset, 0);
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val = tr32(offset);
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/* Test the read-only and read/write bits. */
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if (((val & read_mask) != read_val) || (val & write_mask))
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goto out;
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/* Write ones to all the bits defined by RdMask and WrMask, then
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* make sure the read-only bits are not changed and the
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* read/write bits are all ones.
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*/
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tw32(offset, read_mask | write_mask);
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val = tr32(offset);
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/* Test the read-only bits. */
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if ((val & read_mask) != read_val)
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goto out;
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/* Test the read/write bits. */
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if ((val & write_mask) != write_mask)
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goto out;
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tw32(offset, save_val);
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}
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return 0;
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out:
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printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
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tw32(offset, save_val);
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return -EIO;
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}
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static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
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u64 *data)
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{
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@ -7322,6 +7535,34 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
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etest->flags |= ETH_TEST_FL_FAILED;
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data[1] = 1;
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}
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if (etest->flags & ETH_TEST_FL_OFFLINE) {
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if (netif_running(dev))
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tg3_netif_stop(tp);
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spin_lock_irq(&tp->lock);
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spin_lock(&tp->tx_lock);
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tg3_halt(tp, RESET_KIND_SUSPEND, 1);
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tg3_nvram_lock(tp);
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tg3_halt_cpu(tp, RX_CPU_BASE);
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
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tg3_halt_cpu(tp, TX_CPU_BASE);
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tg3_nvram_unlock(tp);
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if (tg3_test_registers(tp) != 0) {
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etest->flags |= ETH_TEST_FL_FAILED;
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data[2] = 1;
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}
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tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
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if (netif_running(dev)) {
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tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
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tg3_init_hw(tp);
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tg3_netif_start(tp);
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}
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spin_unlock(&tp->tx_lock);
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spin_unlock_irq(&tp->lock);
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}
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}
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static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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