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sh: Drop associative writes for SH-4 cache flushes. 

When flushing/invalidating the icache/dcache via the memory-mapped IC/OC
address arrays, the associative bit should only be used in conjunction with
virtual addresses. However, we currently flush cache lines based on physical
address, so stop using the associative bit.

It is a better strategy to use non-associative writes (and physical tags) for
flushing the caches anyway, because flushing by virtual address (as with the
A-bit set) requires a valid TLB entry for that virtual address. If one does not
exist in the TLB no exception is generated and the flush is silently ignored.

This is also future-proofing for SH-4A parts which are gradually phasing out
associative writes to the cache array due to the aforementioned case of certain
flushes silently turning in to nops.

Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
wifi-calibration
Matt Fleming 2009-12-04 16:18:11 +09:00 committed by Paul Mundt
parent 7e01c94998
commit a781d1e5ff
1 changed files with 2 additions and 2 deletions
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4
arch/sh/mm/cache-sh4.c
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@ -98,7 +98,7 @@ static inline void flush_cache_one(unsigned long start, unsigned long phys)
exec_offset = cached_to_uncached;
local_irq_save(flags);
__flush_cache_one(start | SH_CACHE_ASSOC, phys, exec_offset);
__flush_cache_one(start, phys, exec_offset);
local_irq_restore(flags);
}
@ -123,7 +123,7 @@ static void sh4_flush_dcache_page(void *arg)
/* Loop all the D-cache */
n = boot_cpu_data.dcache.n_aliases;
for (i = 0; i <= n; i++, addr += PAGE_SIZE)
for (i = 0; i < n; i++, addr += PAGE_SIZE)
flush_cache_one(addr, phys);
}