drm/i915/guc: Drop guc2host/host2guc from names
To facilitate code reorganization we are renaming everything that contains guc2host or host2guc. host2guc_action() and host2guc_action_response() become guc_send() and guc_recv() respectively. Other host2guc_*() functions become simply guc_*(). Other entities are renamed basing on context they appear in: - HOST2GUC_ACTIONS_& become INTEL_GUC_ACTION_* - HOST2GUC_{INTERRUPT,TRIGGER} become GUC_SEND_{INTERRUPT,TRIGGER} - GUC2HOST_STATUS_* become INTEL_GUC_STATUS_* - GUC2HOST_MSG_* become INTEL_GUC_RECV_MSG_* - action_lock becomes send_mutex v2: drop unnecessary backslashes and use BIT() instead of '<<' v3: shortened enum names and INTEL_GUC_STATUS_* Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiarski@intel.com> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480096777-12573-3-git-send-email-arkadiusz.hiler@intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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commit
a80bc45ff0
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@ -100,8 +100,8 @@
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GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \
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GUC_ENABLE_MIA_CLOCK_GATING)
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#define HOST2GUC_INTERRUPT _MMIO(0xc4c8)
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#define HOST2GUC_TRIGGER (1<<0)
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#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
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#define GUC_SEND_TRIGGER (1<<0)
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#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
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#define GEN8_DRB_VALID (1<<0)
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@ -49,7 +49,7 @@
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* Firmware writes a success/fail code back to the action register after
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* processes the request. The kernel driver polls waiting for this update and
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* then proceeds.
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* See host2guc_action()
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* See guc_send()
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*
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* Doorbells:
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* Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
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@ -69,15 +69,14 @@
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* Read GuC command/status register (SOFT_SCRATCH_0)
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* Return true if it contains a response rather than a command
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*/
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static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
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u32 *status)
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static inline bool guc_recv(struct drm_i915_private *dev_priv, u32 *status)
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{
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u32 val = I915_READ(SOFT_SCRATCH(0));
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*status = val;
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return GUC2HOST_IS_RESPONSE(val);
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return INTEL_GUC_RECV_IS_RESPONSE(val);
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}
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static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
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static int guc_send(struct intel_guc *guc, u32 *data, u32 len)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 status;
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@ -87,7 +86,7 @@ static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
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if (WARN_ON(len < 1 || len > 15))
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return -EINVAL;
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mutex_lock(&guc->action_lock);
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mutex_lock(&guc->send_mutex);
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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dev_priv->guc.action_count += 1;
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@ -98,17 +97,17 @@ static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
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POSTING_READ(SOFT_SCRATCH(i - 1));
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I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
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I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
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/*
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* Fast commands should complete in less than 10us, so sample quickly
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* up to that length of time, then switch to a slower sleep-wait loop.
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* No HOST2GUC command should ever take longer than 10ms.
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* No INTEL_GUC_ACTION command should ever take longer than 10ms.
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*/
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ret = wait_for_us(host2guc_action_response(dev_priv, &status), 10);
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ret = wait_for_us(guc_recv(dev_priv, &status), 10);
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if (ret)
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ret = wait_for(host2guc_action_response(dev_priv, &status), 10);
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if (status != GUC2HOST_STATUS_SUCCESS) {
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ret = wait_for(guc_recv(dev_priv, &status), 10);
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if (status != INTEL_GUC_STATUS_SUCCESS) {
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/*
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* Either the GuC explicitly returned an error (which
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* we convert to -EIO here) or no response at all was
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@ -126,7 +125,7 @@ static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
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dev_priv->guc.action_status = status;
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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mutex_unlock(&guc->action_lock);
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mutex_unlock(&guc->send_mutex);
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return ret;
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}
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@ -135,35 +134,35 @@ static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
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* Tell the GuC to allocate or deallocate a specific doorbell
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*/
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static int host2guc_allocate_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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static int guc_allocate_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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u32 data[2];
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data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
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data[0] = INTEL_GUC_ACTION_ALLOCATE_DOORBELL;
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data[1] = client->ctx_index;
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return host2guc_action(guc, data, 2);
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return guc_send(guc, data, 2);
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}
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static int host2guc_release_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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static int guc_release_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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u32 data[2];
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data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
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data[0] = INTEL_GUC_ACTION_DEALLOCATE_DOORBELL;
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data[1] = client->ctx_index;
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return host2guc_action(guc, data, 2);
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return guc_send(guc, data, 2);
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}
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static int host2guc_sample_forcewake(struct intel_guc *guc,
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struct i915_guc_client *client)
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static int guc_sample_forcewake(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 data[2];
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data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
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data[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
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data[1] = 0;
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@ -171,36 +170,36 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
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/* bit 0 and 1 are for Render and Media domain separately */
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data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
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return host2guc_action(guc, data, ARRAY_SIZE(data));
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return guc_send(guc, data, ARRAY_SIZE(data));
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}
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static int host2guc_logbuffer_flush_complete(struct intel_guc *guc)
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static int guc_logbuffer_flush_complete(struct intel_guc *guc)
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{
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u32 data[1];
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data[0] = HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;
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data[0] = INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE;
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return host2guc_action(guc, data, 1);
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return guc_send(guc, data, 1);
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}
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static int host2guc_force_logbuffer_flush(struct intel_guc *guc)
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static int guc_force_logbuffer_flush(struct intel_guc *guc)
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{
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u32 data[2];
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data[0] = HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH;
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data[0] = INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH;
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data[1] = 0;
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return host2guc_action(guc, data, 2);
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return guc_send(guc, data, 2);
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}
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static int host2guc_logging_control(struct intel_guc *guc, u32 control_val)
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static int guc_logging_control(struct intel_guc *guc, u32 control_val)
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{
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u32 data[2];
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data[0] = HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING;
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data[0] = INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING;
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data[1] = control_val;
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return host2guc_action(guc, data, 2);
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return guc_send(guc, data, 2);
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}
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/*
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@ -226,7 +225,7 @@ static int guc_update_doorbell_id(struct intel_guc *guc,
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test_bit(client->doorbell_id, doorbell_bitmap)) {
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/* Deactivate the old doorbell */
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doorbell->db_status = GUC_DOORBELL_DISABLED;
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(void)host2guc_release_doorbell(guc, client);
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(void)guc_release_doorbell(guc, client);
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__clear_bit(client->doorbell_id, doorbell_bitmap);
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}
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@ -249,7 +248,7 @@ static int guc_update_doorbell_id(struct intel_guc *guc,
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__set_bit(new_id, doorbell_bitmap);
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doorbell->cookie = 0;
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doorbell->db_status = GUC_DOORBELL_ENABLED;
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return host2guc_allocate_doorbell(guc, client);
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return guc_allocate_doorbell(guc, client);
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}
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static int guc_init_doorbell(struct intel_guc *guc,
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@ -298,7 +297,7 @@ select_doorbell_register(struct intel_guc *guc, uint32_t priority)
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* Select, assign and relase doorbell cachelines
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*
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* These functions track which doorbell cachelines are in use.
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* The data they manipulate is protected by the host2guc lock.
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* The data they manipulate is protected by the guc_send lock.
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*/
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static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
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@ -1500,7 +1499,7 @@ int i915_guc_submission_init(struct drm_i915_private *dev_priv)
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guc->ctx_pool_vma = vma;
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ida_init(&guc->ctx_ids);
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mutex_init(&guc->action_lock);
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mutex_init(&guc->send_mutex);
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guc_log_create(guc);
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guc_addon_create(guc);
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@ -1526,7 +1525,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
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}
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guc->execbuf_client = client;
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host2guc_sample_forcewake(guc, client);
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guc_sample_forcewake(guc, client);
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guc_init_doorbell_hw(guc);
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/* Take over from manual control of ELSP (execlists) */
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@ -1590,13 +1589,13 @@ int intel_guc_suspend(struct drm_device *dev)
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ctx = dev_priv->kernel_context;
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data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
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data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
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/* any value greater than GUC_POWER_D0 */
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data[1] = GUC_POWER_D1;
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/* first page is shared data with GuC */
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data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
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return host2guc_action(guc, data, ARRAY_SIZE(data));
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return guc_send(guc, data, ARRAY_SIZE(data));
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}
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@ -1619,12 +1618,12 @@ int intel_guc_resume(struct drm_device *dev)
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ctx = dev_priv->kernel_context;
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data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
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data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
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data[1] = GUC_POWER_D0;
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/* first page is shared data with GuC */
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data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
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return host2guc_action(guc, data, ARRAY_SIZE(data));
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return guc_send(guc, data, ARRAY_SIZE(data));
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}
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void i915_guc_capture_logs(struct drm_i915_private *dev_priv)
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* time, so get/put should be really quick.
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*/
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intel_runtime_pm_get(dev_priv);
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host2guc_logbuffer_flush_complete(&dev_priv->guc);
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guc_logbuffer_flush_complete(&dev_priv->guc);
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intel_runtime_pm_put(dev_priv);
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}
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@ -1653,7 +1652,7 @@ void i915_guc_flush_logs(struct drm_i915_private *dev_priv)
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flush_work(&dev_priv->guc.log.flush_work);
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/* Ask GuC to update the log buffer state */
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host2guc_force_logbuffer_flush(&dev_priv->guc);
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guc_force_logbuffer_flush(&dev_priv->guc);
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/* GuC would have updated log buffer by now, so capture it */
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i915_guc_capture_logs(dev_priv);
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@ -1694,9 +1693,9 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
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if (!log_param.logging_enabled && (i915.guc_log_level < 0))
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return 0;
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ret = host2guc_logging_control(&dev_priv->guc, log_param.value);
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ret = guc_logging_control(&dev_priv->guc, log_param.value);
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if (ret < 0) {
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DRM_DEBUG_DRIVER("host2guc action failed %d\n", ret);
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DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
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return ret;
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}
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@ -1683,8 +1683,8 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
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u32 msg, flush;
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msg = I915_READ(SOFT_SCRATCH(15));
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flush = msg & (GUC2HOST_MSG_CRASH_DUMP_POSTED |
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GUC2HOST_MSG_FLUSH_LOG_BUFFER);
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flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
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INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
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if (flush) {
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/* Clear the message bits that are handled */
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I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
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@ -489,18 +489,18 @@ union guc_log_control {
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} __packed;
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/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
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enum host2guc_action {
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HOST2GUC_ACTION_DEFAULT = 0x0,
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HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
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HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
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HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
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HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
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HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
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HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
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HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
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HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
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HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
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HOST2GUC_ACTION_LIMIT
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enum intel_guc_action {
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INTEL_GUC_ACTION_DEFAULT = 0x0,
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INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
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INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
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INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
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INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
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INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
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INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
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INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
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INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
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INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
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INTEL_GUC_ACTION_LIMIT
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};
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/*
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@ -509,22 +509,22 @@ enum host2guc_action {
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* by the fact that all the MASK bits are set. The remaining bits
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* give more detail.
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*/
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#define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000)
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#define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK)
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#define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x))
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#define INTEL_GUC_RECV_MASK ((u32)0xF0000000)
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#define INTEL_GUC_RECV_IS_RESPONSE(x) ((u32)(x) >= INTEL_GUC_RECV_MASK)
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#define INTEL_GUC_RECV_STATUS(x) (INTEL_GUC_RECV_MASK | (x))
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/* GUC will return status back to SOFT_SCRATCH_O_REG */
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enum guc2host_status {
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GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0),
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GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10),
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GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20),
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GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000)
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enum intel_guc_status {
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INTEL_GUC_STATUS_SUCCESS = INTEL_GUC_RECV_STATUS(0x0),
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INTEL_GUC_STATUS_ALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x10),
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INTEL_GUC_STATUS_DEALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x20),
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INTEL_GUC_STATUS_GENERIC_FAIL = INTEL_GUC_RECV_STATUS(0x0000F000)
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};
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/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
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enum guc2host_message {
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GUC2HOST_MSG_CRASH_DUMP_POSTED = (1 << 1),
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GUC2HOST_MSG_FLUSH_LOG_BUFFER = (1 << 3)
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enum intel_guc_recv_message {
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INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
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INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
|
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};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -142,7 +142,7 @@ struct intel_guc {
|
|||
struct intel_guc_fw guc_fw;
|
||||
struct intel_guc_log log;
|
||||
|
||||
/* GuC2Host interrupt related state */
|
||||
/* intel_guc_recv interrupt related state */
|
||||
bool interrupts_enabled;
|
||||
|
||||
struct i915_vma *ads_vma;
|
||||
|
@ -164,8 +164,8 @@ struct intel_guc {
|
|||
uint64_t submissions[I915_NUM_ENGINES];
|
||||
uint32_t last_seqno[I915_NUM_ENGINES];
|
||||
|
||||
/* To serialize the Host2GuC actions */
|
||||
struct mutex action_lock;
|
||||
/* To serialize the intel_guc_send actions */
|
||||
struct mutex send_mutex;
|
||||
};
|
||||
|
||||
/* intel_guc_loader.c */
|
||||
|
|
Loading…
Reference in a new issue