Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc: Fix build on some non-freescale platforms powerpc/powernv: Fix PCI resource handling powerpc/crash: Fix build error without SMP powerpc/cpuidle: Make it a bool, not a tristate powerpc/85xx: Add dr_mode property in USB nodes powerpc/85xx: Enable USB2 controller node for P1020RDB powerpc/85xx: Fix cmd12 bug and add the chip compatible for eSDHC arch/powerpc/sysdev/fsl_pci.c: add missing iounmap powerpc: fix compile error with 85xx/p1022_ds.c
This commit is contained in:
commit
a86b4ad6da
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@ -236,6 +236,10 @@
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};
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/include/ "pq3-esdhc-0.dtsi"
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sdhc@2e000 {
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compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
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};
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/include/ "pq3-sec3.0-0.dtsi"
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/include/ "pq3-mpic.dtsi"
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/include/ "pq3-mpic-timer-B.dtsi"
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@ -158,7 +158,8 @@
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/include/ "pq3-usb2-dr-0.dtsi"
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/include/ "pq3-esdhc-0.dtsi"
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sdhc@2e000 {
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fsl,sdhci-auto-cmd12;
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compatible = "fsl,p1010-esdhc", "fsl,esdhc";
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sdhci,auto-cmd12;
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};
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/include/ "pq3-sec4.4-0.dtsi"
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@ -145,6 +145,10 @@
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/include/ "pq3-usb2-dr-1.dtsi"
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/include/ "pq3-esdhc-0.dtsi"
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sdhc@2e000 {
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compatible = "fsl,p1020-esdhc", "fsl,esdhc";
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sdhci,auto-cmd12;
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};
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/include/ "pq3-sec3.3-0.dtsi"
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/include/ "pq3-mpic.dtsi"
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@ -203,7 +203,8 @@
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/include/ "pq3-esdhc-0.dtsi"
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sdhc@2e000 {
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fsl,sdhci-auto-cmd12;
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compatible = "fsl,p1022-esdhc", "fsl,esdhc";
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sdhci,auto-cmd12;
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};
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/include/ "pq3-sec3.3-0.dtsi"
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@ -182,6 +182,10 @@
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/include/ "pq3-etsec1-1.dtsi"
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/include/ "pq3-etsec1-2.dtsi"
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/include/ "pq3-esdhc-0.dtsi"
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sdhc@2e000 {
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compatible = "fsl,p2020-esdhc", "fsl,esdhc";
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};
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/include/ "pq3-sec3.1-0.dtsi"
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/include/ "pq3-mpic.dtsi"
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/include/ "pq3-mpic-timer-B.dtsi"
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@ -1,7 +1,7 @@
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/*
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* P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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* Copyright 2011-2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -190,17 +190,16 @@
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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/* USB2 is shared with localbus, so it must be disabled
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by default. We can't put 'status = "disabled";' here
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since U-Boot doesn't clear the status property when
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it enables USB2. OTOH, U-Boot does create a new node
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when there isn't any. So, just comment it out.
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/* USB2 is shared with localbus. It is used
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only in case of SPI and SD boot after
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appropriate device-tree fixup done by uboot */
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usb@23000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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*/
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mdio@24000 {
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phy0: ethernet-phy@0 {
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@ -1,7 +1,7 @@
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/*
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* P1021 MDS Device Tree Source
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*
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* Copyright 2010 Freescale Semiconductor Inc.
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* Copyright 2010,2012 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -151,6 +151,7 @@
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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mdio@24000 {
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@ -1,7 +1,7 @@
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/*
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* P2020DS Device Tree Source stub (no addresses or top-level ranges)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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* Copyright 2011-2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -134,6 +134,7 @@
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&board_soc {
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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mdio@24520 {
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@ -1,7 +1,7 @@
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/*
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* P2020 RDB Device Tree Source
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*
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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* Copyright 2009-2012 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -197,6 +197,7 @@
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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mdio@24520 {
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@ -46,7 +46,6 @@
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/* This keeps a track of which one is the crashing cpu. */
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int crashing_cpu = -1;
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static atomic_t cpus_in_crash;
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static int time_to_dump;
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#define CRASH_HANDLER_MAX 3
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#ifdef CONFIG_SMP
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static atomic_t cpus_in_crash;
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void crash_ipi_callback(struct pt_regs *regs)
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{
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static cpumask_t cpus_state_saved = CPU_MASK_NONE;
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@ -442,8 +442,10 @@ static void __init fixup_port_irq(int index,
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port->irq = virq;
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#ifdef CONFIG_SERIAL_8250_FSL
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if (of_device_is_compatible(np, "fsl,ns16550"))
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port->handle_irq = fsl8250_handle_irq;
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#endif
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}
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static void __init fixup_port_pio(int index,
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@ -25,6 +25,7 @@
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/udbg.h>
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#include <asm/fsl_guts.h>
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#include "smp.h"
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@ -204,11 +204,10 @@ static void __devinit pnv_ioda_offset_bus(struct pci_bus *bus,
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pr_devel(" -> OBR %s [%x] +%016llx\n",
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bus->self ? pci_name(bus->self) : "root", flags, offset);
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for (i = 0; i < 2; i++) {
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r = bus->resource[i];
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pci_bus_for_each_resource(bus, r, i) {
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if (r && (r->flags & flags)) {
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bus->resource[i]->start += offset;
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bus->resource[i]->end += offset;
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r->start += offset;
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r->end += offset;
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}
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}
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list_for_each_entry(dev, &bus->devices, bus_list)
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* assignment algorithm is going to be uber-trivial for now, we
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* can try to be smarter later at filling out holes.
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*/
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start = bus->self ? 0 : bus->resource[bres]->start;
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/* Don't hand out IO 0 */
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if ((flags & IORESOURCE_IO) && !bus->self)
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start += 0x1000;
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if (bus->self) {
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/* No offset for downstream bridges */
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start = 0;
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} else {
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/* Offset from the root */
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if (flags & IORESOURCE_IO)
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/* Don't hand out IO 0 */
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start = hose->io_resource.start + 0x1000;
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else
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start = hose->mem_resources[0].start;
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}
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while(!list_empty(&head)) {
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w = list_first_entry(&head, struct resource_wrap, link);
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list_del(&w->link);
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empty:
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/* Only setup P2P's, not the PHB itself */
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if (bus->self) {
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WARN_ON(bus->resource[bres] == NULL);
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bus->resource[bres]->start = 0;
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bus->resource[bres]->flags = (*size) ? flags : 0;
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bus->resource[bres]->end = (*size) ? (*size - 1) : 0;
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struct resource *res = bus->resource[bres];
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/* Clear prefetch bus resources for now */
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bus->resource[2]->flags = 0;
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if (WARN_ON(res == NULL))
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return;
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/*
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* FIXME: We should probably export and call
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* pci_bridge_check_ranges() to properly re-initialize
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* the PCI portion of the flags here, and to detect
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* what the bridge actually supports.
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*/
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res->start = 0;
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res->flags = (*size) ? flags : 0;
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res->end = (*size) ? (*size - 1) : 0;
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}
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pr_devel("<- CBR %s [%x] *size=%016llx *align=%016llx\n",
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@ -122,7 +122,7 @@ config DTL
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Say N if you are unsure.
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config PSERIES_IDLE
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tristate "Cpuidle driver for pSeries platforms"
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bool "Cpuidle driver for pSeries platforms"
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depends on CPU_IDLE
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depends on PPC_PSERIES
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default y
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@ -205,12 +205,12 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
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if (paddr_hi == paddr_lo) {
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pr_err("%s: No outbound window space\n", name);
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return ;
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goto out;
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}
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if (paddr_lo == 0) {
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pr_err("%s: No space for inbound window\n", name);
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return ;
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goto out;
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}
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/* setup PCSRBAR/PEXCSRBAR */
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(u64)hose->dma_window_size);
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}
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out:
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iounmap(pci);
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}
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Loading…
Reference in a new issue