pinctrl: sh-pfc: r8a77965: Add support for INTC-EX IRQ pins
Most pins on the R8A77965 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Based on a similar patch for the R8A7795 PFC driver by Magnus Damm <damm+renesas@opensource.se>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -1661,6 +1661,51 @@ static const unsigned int avb_avtp_capture_b_pins[] = {
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static const unsigned int avb_avtp_capture_b_mux[] = {
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AVB_AVTP_CAPTURE_B_MARK,
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};
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/* - INTC-EX ---------------------------------------------------------------- */
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static const unsigned int intc_ex_irq0_pins[] = {
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/* IRQ0 */
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RCAR_GP_PIN(2, 0),
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};
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static const unsigned int intc_ex_irq0_mux[] = {
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IRQ0_MARK,
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};
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static const unsigned int intc_ex_irq1_pins[] = {
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/* IRQ1 */
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RCAR_GP_PIN(2, 1),
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};
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static const unsigned int intc_ex_irq1_mux[] = {
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IRQ1_MARK,
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};
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static const unsigned int intc_ex_irq2_pins[] = {
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/* IRQ2 */
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RCAR_GP_PIN(2, 2),
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};
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static const unsigned int intc_ex_irq2_mux[] = {
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IRQ2_MARK,
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};
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static const unsigned int intc_ex_irq3_pins[] = {
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/* IRQ3 */
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RCAR_GP_PIN(2, 3),
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};
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static const unsigned int intc_ex_irq3_mux[] = {
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IRQ3_MARK,
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};
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static const unsigned int intc_ex_irq4_pins[] = {
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/* IRQ4 */
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RCAR_GP_PIN(2, 4),
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};
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static const unsigned int intc_ex_irq4_mux[] = {
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IRQ4_MARK,
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};
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static const unsigned int intc_ex_irq5_pins[] = {
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/* IRQ5 */
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RCAR_GP_PIN(2, 5),
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};
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static const unsigned int intc_ex_irq5_mux[] = {
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IRQ5_MARK,
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};
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/* - SCIF0 ------------------------------------------------------------------ */
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static const unsigned int scif0_data_pins[] = {
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/* RX, TX */
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@ -1883,6 +1928,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(avb_avtp_capture_a),
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SH_PFC_PIN_GROUP(avb_avtp_match_b),
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SH_PFC_PIN_GROUP(avb_avtp_capture_b),
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SH_PFC_PIN_GROUP(intc_ex_irq0),
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SH_PFC_PIN_GROUP(intc_ex_irq1),
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SH_PFC_PIN_GROUP(intc_ex_irq2),
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SH_PFC_PIN_GROUP(intc_ex_irq3),
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SH_PFC_PIN_GROUP(intc_ex_irq4),
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SH_PFC_PIN_GROUP(intc_ex_irq5),
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SH_PFC_PIN_GROUP(scif0_data),
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SH_PFC_PIN_GROUP(scif0_clk),
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SH_PFC_PIN_GROUP(scif0_ctrl),
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@ -1927,6 +1978,15 @@ static const char * const avb_groups[] = {
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"avb_avtp_capture_b",
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};
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static const char * const intc_ex_groups[] = {
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"intc_ex_irq0",
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"intc_ex_irq1",
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"intc_ex_irq2",
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"intc_ex_irq3",
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"intc_ex_irq4",
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"intc_ex_irq5",
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};
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static const char * const scif0_groups[] = {
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"scif0_data",
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"scif0_clk",
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@ -1978,6 +2038,7 @@ static const char * const scif_clk_groups[] = {
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static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(avb),
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SH_PFC_FUNCTION(intc_ex),
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SH_PFC_FUNCTION(scif0),
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SH_PFC_FUNCTION(scif1),
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SH_PFC_FUNCTION(scif2),
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