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MLK-18861: mx8qxp: Add the missing LCDIF clocks to clock driver 

Add LCDIF PLL resource and clocks, and power domain for it.
Add Pixel link clocks and set it from bypass path.
Muxes were added so that the slices can choose the bypass input
(lcd_pxl_bypass_div and elcdif_pll_div).

clk summary example:

lcd_pxl_bypass_div                       2            2    24000000
   lcd_pxl_sel                           1            1    24000000
      lcd_pxl_div                        1            1    24000000
         lcd_pxl_clk                     1            1    24000000
elcdif_pll_div                           1            1   792000000
   elcdif_pll                            2            2   792000000
      lcd_sel                            1            1   792000000
         lcd_div                         1            1    79200000
            lcd_clk                      1            1    79200000

Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
pull/10/head
Adriana Reus 2018-07-11 17:26:57 +03:00 committed by Jason Liu
parent 1fee453256
commit a8d539e9dd
6 changed files with 50 additions and 6 deletions
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13
arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
View File

@ -979,10 +979,19 @@
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lcd0: PD_DMA_LCD_0 {
reg = <SC_R_LCD_0>;
pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
reg = <SC_R_ELCDIF_PLL>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma_lcd0: PD_DMA_LCD_0 {
reg = <SC_R_LCD_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma_elcdif_pll>;
};
};
};

26
drivers/clk/imx/clk-imx8qxp.c
View File

@ -139,6 +139,22 @@ static const char *pll0_sels[] = {
"dummy",
};
static const char *lcd_pxl_sels[] = {
"dummy",
"dummy",
"dummy",
"dummy",
"lcd_pxl_bypass_div",
};
static const char *lcd_sels[] = {
"dummy",
"dummy",
"dummy",
"dummy",
"elcdif_pll",
};
static struct clk *clks[IMX8QXP_CLK_END];
static struct clk_onecell_data clk_data;
@ -171,10 +187,12 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
/* User Defined PLLs dividers */
clks[IMX8QXP_AUD_PLL0_DIV] = imx_clk_divider_scu("audio_pll0_div", SC_R_AUDIO_PLL_0, SC_PM_CLK_PLL);
clks[IMX8QXP_AUD_PLL1_DIV] = imx_clk_divider_scu("audio_pll1_div", SC_R_AUDIO_PLL_1, SC_PM_CLK_PLL);
clks[IMX8QXP_ELCDIF_PLL_DIV] = imx_clk_divider_scu("elcdif_pll_div", SC_R_ELCDIF_PLL, SC_PM_CLK_PLL);
/* User Defined PLLs clocks */
clks[IMX8QXP_AUD_PLL0] = imx_clk_gate_scu("audio_pll0_clk", "audio_pll0_div", SC_R_AUDIO_PLL_0, SC_PM_CLK_PLL, NULL, 0, 0);
clks[IMX8QXP_AUD_PLL1] = imx_clk_gate_scu("audio_pll1_clk", "audio_pll1_div", SC_R_AUDIO_PLL_1, SC_PM_CLK_PLL, NULL, 0, 0);
clks[IMX8QXP_ELCDIF_PLL] = imx_clk_gate_scu("elcdif_pll", "elcdif_pll_div", SC_R_ELCDIF_PLL, SC_PM_CLK_PLL, NULL, 0, 0);
clks[IMX8QXP_IPG_DMA_CLK_ROOT] = imx_clk_fixed("ipg_dma_clk_root", SC_120MHZ);
clks[IMX8QXP_IPG_AUD_CLK_ROOT] = imx_clk_fixed("ipg_aud_clk_root", SC_150MHZ);
@ -360,7 +378,13 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX8QXP_PWM_DIV] = imx_clk_divider_scu("pwm_div", SC_R_LCD_0_PWM_0, SC_PM_CLK_PER);
clks[IMX8QXP_PWM_CLK] = imx_clk_gate_scu("pwm_clk", "pwm_div", SC_R_LCD_0_PWM_0, SC_PM_CLK_PER, (void __iomem *)(PWM_LPCG), 0, 0);
clks[IMX8QXP_LCD_IPG_CLK] = imx_clk_gate2_scu("lcd_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LCD_LPCG), 16, FUNCTION_NAME(PD_DMA_LCD_0));
clks[IMX8QXP_LCD_DIV] = imx_clk_divider_scu("lcd_div", SC_R_LCD_0, SC_PM_CLK_PER);
clks[IMX8QXP_LCD_PXL_BYPASS_DIV] = imx_clk_divider_scu("lcd_pxl_bypass_div", SC_R_LCD_0, SC_PM_CLK_BYPASS);
clks[IMX8QXP_LCD_PXL_SEL] = imx_clk_mux2_scu("lcd_pxl_sel", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), SC_R_LCD_0, SC_PM_CLK_MISC0);
clks[IMX8QXP_LCD_PXL_DIV] = imx_clk_divider2_scu("lcd_pxl_div", "lcd_pxl_sel", SC_R_LCD_0, SC_PM_CLK_MISC0);
clks[IMX8QXP_LCD_PXL_CLK] = imx_clk_gate_scu("lcd_pxl_clk", "lcd_pxl_div", SC_R_LCD_0, SC_PM_CLK_MISC0, NULL, 0, 0);
clks[IMX8QXP_LCD_SEL] = imx_clk_mux2_scu("lcd_sel", lcd_sels, ARRAY_SIZE(lcd_sels), SC_R_LCD_0, SC_PM_CLK_PER);
clks[IMX8QXP_LCD_DIV] = imx_clk_divider2_scu("lcd_div", "lcd_sel", SC_R_LCD_0, SC_PM_CLK_PER);
clks[IMX8QXP_LCD_CLK] = imx_clk_gate_scu("lcd_clk", "lcd_div", SC_R_LCD_0, SC_PM_CLK_PER, (void __iomem *)(LCD_LPCG), 0, 0);
/* Connectivity */

12
include/dt-bindings/clock/imx8qxp-clock.h
View File

@ -589,5 +589,15 @@
#define IMX8QXP_LSIO_MU5A_IPG_S_CLK 528
#define IMX8QXP_LSIO_MU5A_IPG_CLK 529
#define IMX8QXP_CLK_END 530
/* LCD part2 */
#define IMX8QXP_LCD_PXL_BYPASS_DIV 530
#define IMX8QXP_LCD_PXL_SEL 531
#define IMX8QXP_LCD_PXL_DIV 532
#define IMX8QXP_LCD_PXL_CLK 533
#define IMX8QXP_ELCDIF_PLL_DIV 534
#define IMX8QXP_ELCDIF_PLL 535
#define IMX8QXP_LCD_SEL 536
#define IMX8QXP_CLK_END 537
#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */

1
include/dt-bindings/soc/imx8_pd.h
View File

@ -65,6 +65,7 @@
#define PD_DMA_CAN_2 dma_flexcan2
#define PD_DMA_PWM_0 dma_pwm0
#define PD_DMA_LCD_0 dma_lcd0
#define PD_DMA_ELCDIF_PLL dma_elcdif_pll
#define PD_HSIO hsio_power_domain
#define PD_HSIO_PCIE_A hsio_pcie0

2
include/dt-bindings/soc/imx_rsrc.h
View File

@ -336,7 +336,7 @@
#define SC_R_SAI_2 320
#define SC_R_IRQSTR_SCU2 321
#define SC_R_IRQSTR_DSP 322
#define SC_R_UNUSED5 323
#define SC_R_ELCDIF_PLL 323
#define SC_R_UNUSED6 324
#define SC_R_AUDIO_PLL_0 325
#define SC_R_PI_0 326

2
include/soc/imx8/sc/types.h
View File

@ -489,7 +489,7 @@ typedef enum sc_rsrc_e {
SC_R_SAI_2 = 320,
SC_R_IRQSTR_SCU2 = 321,
SC_R_IRQSTR_DSP = 322,
SC_R_UNUSED5 = 323,
SC_R_ELCDIF_PLL = 323,
SC_R_UNUSED6 = 324,
SC_R_AUDIO_PLL_0 = 325,
SC_R_PI_0 = 326,