arm64: Move BP hardening to check_and_switch_context
We call arm64_apply_bp_hardening() from post_ttbr_update_workaround, which has the unexpected consequence of being triggered on every exception return to userspace when ARM64_SW_TTBR0_PAN is selected, even if no context switch actually occured. This is a bit suboptimal, and it would be more logical to only invalidate the branch predictor when we actually switch to a different mm. In order to solve this, move the call to arm64_apply_bp_hardening() into check_and_switch_context(), where we're guaranteed to pick a different mm context. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -234,6 +234,9 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
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raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
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switch_mm_fastpath:
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arm64_apply_bp_hardening();
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/*
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* Defer TTBR0_EL1 setting for user threads to uaccess_enable() when
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* emulating PAN.
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@ -249,8 +252,6 @@ asmlinkage void post_ttbr_update_workaround(void)
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"ic iallu; dsb nsh; isb",
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ARM64_WORKAROUND_CAVIUM_27456,
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CONFIG_CAVIUM_ERRATUM_27456));
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arm64_apply_bp_hardening();
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}
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static int asids_init(void)
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