ARM: exynos: move exynos4210-combiner to drivers/irqchip
Exynos boot is broken with commit 0529e315 (ARM: use common irqchip_init
for GIC init). This commit split the irqchip initialization into 2 calls
to of_irq_init. This does not work because of_irq_init requires interrupt
parents to be in the match list.
Rather than reverting exynos changes, make it do the proper thing by using
IRQCHIP_DECLARE. This requires moving the combiner code to drivers/irqchip.
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-samsung-soc@vger.kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Rob Herring
Olof Johansson
parent
2aecd7dd2b
commit
a900e5d997
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@ -12,6 +12,7 @@
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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@ -438,218 +439,6 @@ static void __init exynos5_init_clocks(int xtal)
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#endif
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}
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct combiner_chip_data {
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unsigned int irq_offset;
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unsigned int irq_mask;
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void __iomem *base;
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};
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static struct irq_domain *combiner_irq_domain;
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static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
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static inline void __iomem *combiner_base(struct irq_data *data)
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{
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struct combiner_chip_data *combiner_data =
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irq_data_get_irq_chip_data(data);
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return combiner_data->base;
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}
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static void combiner_mask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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}
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static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned int cascade_irq, combiner_irq;
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unsigned long status;
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chained_irq_enter(chip, desc);
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spin_lock(&irq_controller_lock);
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status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
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spin_unlock(&irq_controller_lock);
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status &= chip_data->irq_mask;
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if (status == 0)
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goto out;
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combiner_irq = __ffs(status);
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cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
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if (unlikely(cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip combiner_chip = {
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.name = "COMBINER",
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.irq_mask = combiner_mask_irq,
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.irq_unmask = combiner_unmask_irq,
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};
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static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
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{
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unsigned int max_nr;
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if (soc_is_exynos5250())
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max_nr = EXYNOS5_MAX_COMBINER_NR;
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else
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max_nr = EXYNOS4_MAX_COMBINER_NR;
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if (combiner_nr >= max_nr)
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BUG();
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if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
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BUG();
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irq_set_chained_handler(irq, combiner_handle_cascade_irq);
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}
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static void __init combiner_init_one(unsigned int combiner_nr,
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void __iomem *base)
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{
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combiner_data[combiner_nr].base = base;
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combiner_data[combiner_nr].irq_offset = irq_find_mapping(
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combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
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combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
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/* Disable all interrupts */
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__raw_writel(combiner_data[combiner_nr].irq_mask,
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base + COMBINER_ENABLE_CLEAR);
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}
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#ifdef CONFIG_OF
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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if (d->of_node != controller)
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return -EINVAL;
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if (intsize < 2)
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return -EINVAL;
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*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
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*out_type = 0;
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return 0;
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}
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#else
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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return -EINVAL;
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}
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#endif
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static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
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irq_set_chip_data(irq, &combiner_data[hw >> 3]);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops combiner_irq_domain_ops = {
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.xlate = combiner_irq_domain_xlate,
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.map = combiner_irq_domain_map,
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};
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static void __init combiner_init(void __iomem *combiner_base,
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struct device_node *np)
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{
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int i, irq, irq_base;
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unsigned int max_nr, nr_irq;
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if (np) {
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if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
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pr_warning("%s: number of combiners not specified, "
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"setting default as %d.\n",
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__func__, EXYNOS4_MAX_COMBINER_NR);
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max_nr = EXYNOS4_MAX_COMBINER_NR;
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}
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} else {
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max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
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EXYNOS4_MAX_COMBINER_NR;
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}
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nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
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irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
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if (IS_ERR_VALUE(irq_base)) {
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irq_base = COMBINER_IRQ(0, 0);
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pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
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}
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combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
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&combiner_irq_domain_ops, &combiner_data);
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if (WARN_ON(!combiner_irq_domain)) {
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pr_warning("%s: irq domain init failed\n", __func__);
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return;
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}
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for (i = 0; i < max_nr; i++) {
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combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
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irq = IRQ_SPI(i);
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#ifdef CONFIG_OF
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if (np)
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irq = irq_of_parse_and_map(np, i);
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#endif
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combiner_cascade_irq(i, irq);
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}
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}
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#ifdef CONFIG_OF
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static int __init combiner_of_init(struct device_node *np,
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struct device_node *parent)
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{
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void __iomem *combiner_base;
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combiner_base = of_iomap(np, 0);
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if (!combiner_base) {
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pr_err("%s: failed to map combiner registers\n", __func__);
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return -ENXIO;
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}
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combiner_init(combiner_base, np);
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return 0;
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}
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static const struct of_device_id exynos_dt_irq_match[] = {
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{ .compatible = "samsung,exynos4210-combiner",
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.data = combiner_of_init, },
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{},
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};
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#endif
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void __init exynos4_init_irq(void)
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{
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unsigned int gic_bank_offset;
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@ -659,10 +448,8 @@ void __init exynos4_init_irq(void)
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if (!of_have_populated_dt())
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gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
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#ifdef CONFIG_OF
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else {
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else
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irqchip_init();
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of_irq_init(exynos_dt_irq_match);
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}
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#endif
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if (!of_have_populated_dt())
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@ -680,7 +467,6 @@ void __init exynos5_init_irq(void)
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{
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#ifdef CONFIG_OF
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irqchip_init();
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of_irq_init(exynos_dt_irq_match);
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#endif
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/*
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* The parameters of s5p_init_irq() are for VIC init.
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@ -60,6 +60,9 @@ void exynos4212_register_clocks(void);
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#define exynos4212_register_clocks()
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#endif
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struct device_node;
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void combiner_init(void __iomem *combiner_base, struct device_node *np);
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extern struct smp_operations exynos_smp_ops;
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extern void exynos_cpu_die(unsigned int cpu);
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@ -1,6 +1,7 @@
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obj-$(CONFIG_IRQCHIP) += irqchip.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o
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230
drivers/irqchip/exynos-combiner.c
Normal file
230
drivers/irqchip/exynos-combiner.c
Normal file
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@ -0,0 +1,230 @@
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/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Combiner irqchip for EXYNOS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/mach/irq.h>
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#include <plat/cpu.h>
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#include "irqchip.h"
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct combiner_chip_data {
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unsigned int irq_offset;
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unsigned int irq_mask;
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void __iomem *base;
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};
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static struct irq_domain *combiner_irq_domain;
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static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
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static inline void __iomem *combiner_base(struct irq_data *data)
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{
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struct combiner_chip_data *combiner_data =
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irq_data_get_irq_chip_data(data);
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return combiner_data->base;
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}
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static void combiner_mask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->hwirq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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}
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static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned int cascade_irq, combiner_irq;
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unsigned long status;
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chained_irq_enter(chip, desc);
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spin_lock(&irq_controller_lock);
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status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
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spin_unlock(&irq_controller_lock);
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status &= chip_data->irq_mask;
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if (status == 0)
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goto out;
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combiner_irq = __ffs(status);
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cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
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if (unlikely(cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip combiner_chip = {
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.name = "COMBINER",
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.irq_mask = combiner_mask_irq,
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.irq_unmask = combiner_unmask_irq,
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};
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static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
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{
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unsigned int max_nr;
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if (soc_is_exynos5250())
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max_nr = EXYNOS5_MAX_COMBINER_NR;
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else
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max_nr = EXYNOS4_MAX_COMBINER_NR;
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if (combiner_nr >= max_nr)
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BUG();
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if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
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BUG();
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irq_set_chained_handler(irq, combiner_handle_cascade_irq);
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}
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static void __init combiner_init_one(unsigned int combiner_nr,
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void __iomem *base)
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{
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combiner_data[combiner_nr].base = base;
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combiner_data[combiner_nr].irq_offset = irq_find_mapping(
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combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
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combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
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/* Disable all interrupts */
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__raw_writel(combiner_data[combiner_nr].irq_mask,
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base + COMBINER_ENABLE_CLEAR);
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}
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#ifdef CONFIG_OF
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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if (d->of_node != controller)
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return -EINVAL;
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if (intsize < 2)
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return -EINVAL;
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*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
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*out_type = 0;
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return 0;
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}
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#else
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static int combiner_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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return -EINVAL;
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}
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#endif
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static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
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irq_set_chip_data(irq, &combiner_data[hw >> 3]);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops combiner_irq_domain_ops = {
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.xlate = combiner_irq_domain_xlate,
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.map = combiner_irq_domain_map,
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};
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void __init combiner_init(void __iomem *combiner_base,
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struct device_node *np)
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{
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int i, irq, irq_base;
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unsigned int max_nr, nr_irq;
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if (np) {
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if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
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pr_warning("%s: number of combiners not specified, "
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"setting default as %d.\n",
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__func__, EXYNOS4_MAX_COMBINER_NR);
|
||||
max_nr = EXYNOS4_MAX_COMBINER_NR;
|
||||
}
|
||||
} else {
|
||||
max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
|
||||
EXYNOS4_MAX_COMBINER_NR;
|
||||
}
|
||||
nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
|
||||
|
||||
irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
|
||||
if (IS_ERR_VALUE(irq_base)) {
|
||||
irq_base = COMBINER_IRQ(0, 0);
|
||||
pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
|
||||
}
|
||||
|
||||
combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
|
||||
&combiner_irq_domain_ops, &combiner_data);
|
||||
if (WARN_ON(!combiner_irq_domain)) {
|
||||
pr_warning("%s: irq domain init failed\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < max_nr; i++) {
|
||||
combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
|
||||
irq = IRQ_SPI(i);
|
||||
#ifdef CONFIG_OF
|
||||
if (np)
|
||||
irq = irq_of_parse_and_map(np, i);
|
||||
#endif
|
||||
combiner_cascade_irq(i, irq);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static int __init combiner_of_init(struct device_node *np,
|
||||
struct device_node *parent)
|
||||
{
|
||||
void __iomem *combiner_base;
|
||||
|
||||
combiner_base = of_iomap(np, 0);
|
||||
if (!combiner_base) {
|
||||
pr_err("%s: failed to map combiner registers\n", __func__);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
combiner_init(combiner_base, np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner",
|
||||
combiner_of_init);
|
||||
#endif
|
||||
Loading…
Reference in a new issue