RealView: Base support for the PB11MPCore platform
This patch adds the base files for the PB11MPCore platform support. Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Bahadir Balban
Catalin Marinas
parent
51faf9b5c0
commit
a9b67db504
314
arch/arm/mach-realview/realview_pb11mp.c
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314
arch/arm/mach-realview/realview_pb11mp.c
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/*
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* linux/arch/arm/mach-realview/realview_pb11mp.c
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*
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* Copyright (C) 2008 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/sysdev.h>
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#include <linux/amba/bus.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/leds.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/icst307.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/map.h>
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#include <asm/mach/mmc.h>
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#include <asm/mach/time.h>
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#include <asm/arch/board-pb11mp.h>
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#include <asm/arch/irqs.h>
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#include "core.h"
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#include "clock.h"
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static struct map_desc realview_pb11mp_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
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.pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
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.pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
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.length = SZ_8K,
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.type = MT_DEVICE,
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},
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#ifdef CONFIG_DEBUG_LL
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{
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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#endif
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};
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static void __init realview_pb11mp_map_io(void)
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{
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iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
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}
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/*
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* RealView PB11MPCore AMBA devices
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*/
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#define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ }
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#define GPIO2_DMA { 0, 0 }
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#define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ }
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#define GPIO3_DMA { 0, 0 }
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#define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ }
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#define AACI_DMA { 0x80, 0x81 }
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#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
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#define MMCI0_DMA { 0x84, 0 }
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#define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ }
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#define KMI0_DMA { 0, 0 }
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#define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ }
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#define KMI1_DMA { 0, 0 }
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#define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ }
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#define PB11MP_SMC_DMA { 0, 0 }
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#define MPMC_IRQ { NO_IRQ, NO_IRQ }
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#define MPMC_DMA { 0, 0 }
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#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ }
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#define PB11MP_CLCD_DMA { 0, 0 }
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#define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ }
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#define DMAC_DMA { 0, 0 }
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#define SCTL_IRQ { NO_IRQ, NO_IRQ }
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#define SCTL_DMA { 0, 0 }
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#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ }
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#define PB11MP_WATCHDOG_DMA { 0, 0 }
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#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ }
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#define PB11MP_GPIO0_DMA { 0, 0 }
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#define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ }
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#define GPIO1_DMA { 0, 0 }
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#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ }
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#define PB11MP_RTC_DMA { 0, 0 }
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#define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ }
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#define SCI_DMA { 7, 6 }
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#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ }
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#define PB11MP_UART0_DMA { 15, 14 }
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#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ }
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#define PB11MP_UART1_DMA { 13, 12 }
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#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ }
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#define PB11MP_UART2_DMA { 11, 10 }
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#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ }
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#define PB11MP_UART3_DMA { 0x86, 0x87 }
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#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ }
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#define PB11MP_SSP_DMA { 9, 8 }
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/* FPGA Primecells */
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AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
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AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
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AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
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AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
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AMBA_DEVICE(uart3, "fpga:09", PB11MP_UART3, NULL);
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/* DevChip Primecells */
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AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL);
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AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
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AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL);
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AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, NULL);
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AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
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AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
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AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL);
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AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
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AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL);
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AMBA_DEVICE(uart1, "dev:f2", PB11MP_UART1, NULL);
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AMBA_DEVICE(uart2, "dev:f3", PB11MP_UART2, NULL);
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AMBA_DEVICE(ssp0, "dev:f4", PB11MP_SSP, NULL);
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/* Primecells on the NEC ISSP chip */
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AMBA_DEVICE(clcd, "issp:20", PB11MP_CLCD, &clcd_plat_data);
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AMBA_DEVICE(dmac, "issp:30", DMAC, NULL);
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static struct amba_device *amba_devs[] __initdata = {
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&dmac_device,
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&uart0_device,
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&uart1_device,
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&uart2_device,
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&uart3_device,
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&smc_device,
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&clcd_device,
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&sctl_device,
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&wdog_device,
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&gpio0_device,
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&gpio1_device,
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&gpio2_device,
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&rtc_device,
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&sci0_device,
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&ssp0_device,
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&aaci_device,
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&mmc0_device,
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&kmi0_device,
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&kmi1_device,
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};
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/*
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* RealView PB11MPCore platform devices
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*/
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static struct resource realview_pb11mp_flash_resource[] = {
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[0] = {
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.start = REALVIEW_PB11MP_FLASH0_BASE,
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.end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = REALVIEW_PB11MP_FLASH1_BASE,
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.end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource realview_pb11mp_smsc911x_resources[] = {
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[0] = {
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.start = REALVIEW_PB11MP_ETH_BASE,
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.end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_TC11MP_ETH,
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.end = IRQ_TC11MP_ETH,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device realview_pb11mp_smsc911x_device = {
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.name = "smc911x",
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.id = 0,
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.num_resources = ARRAY_SIZE(realview_pb11mp_smsc911x_resources),
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.resource = realview_pb11mp_smsc911x_resources,
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};
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static void __init gic_init_irq(void)
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{
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unsigned int pldctrl;
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/* new irq mode with no DCC */
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writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
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pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
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pldctrl |= 2 << 22;
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writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
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writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
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/* ARM11MPCore test chip GIC, primary */
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gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
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gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
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gic_cpu_init(0, gic_cpu_base_addr);
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/* board GIC, secondary */
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gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
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gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
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gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
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}
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static void __init realview_pb11mp_timer_init(void)
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{
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timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
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timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
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timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
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timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE);
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twd_size = REALVIEW_TC11MP_TWD_SIZE;
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#endif
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realview_timer_init(IRQ_TC11MP_TIMER0_1);
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}
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static struct sys_timer realview_pb11mp_timer = {
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.init = realview_pb11mp_timer_init,
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};
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static void __init realview_pb11mp_init(void)
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{
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int i;
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/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
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* Bits: .... ...0 0111 1001 0000 .... .... .... */
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l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
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clk_register(&realview_clcd_clk);
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realview_flash_register(realview_pb11mp_flash_resource,
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ARRAY_SIZE(realview_pb11mp_flash_resource));
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platform_device_register(&realview_pb11mp_smsc911x_device);
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platform_device_register(&realview_i2c_device);
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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#ifdef CONFIG_LEDS
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leds_event = realview_leds_event;
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#endif
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}
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MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
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/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
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.phys_io = REALVIEW_PB11MP_UART0_BASE,
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.io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.map_io = realview_pb11mp_map_io,
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.init_irq = gic_init_irq,
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.timer = &realview_pb11mp_timer,
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.init_machine = realview_pb11mp_init,
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MACHINE_END
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186
include/asm-arm/arch-realview/board-pb11mp.h
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186
include/asm-arm/arch-realview/board-pb11mp.h
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@ -0,0 +1,186 @@
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/*
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* include/asm-arm/arch-realview/board-pb11mp.h
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*
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* Copyright (C) 2008 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_BOARD_PB11MP_H
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#define __ASM_ARCH_BOARD_PB11MP_H
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#include <asm/arch/platform.h>
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/*
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* Peripheral addresses
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*/
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#define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */
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#define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */
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#define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */
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#define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */
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#define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
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#define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
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#define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */
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#define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
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#define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
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#define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */
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#define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */
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#define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
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#define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
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#define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */
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#define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */
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#define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
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#define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */
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#define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */
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#define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */
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#define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */
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#define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */
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#define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
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#define REALVIEW_PB11MP_FLASH0_BASE 0x40000000
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#define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M
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#define REALVIEW_PB11MP_FLASH1_BASE 0x44000000
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#define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M
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#define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */
|
||||
#define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */
|
||||
#define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
|
||||
#define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */
|
||||
#define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
|
||||
#define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
|
||||
|
||||
#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74
|
||||
|
||||
/*
|
||||
* PB11MPCore PCI regions
|
||||
*/
|
||||
#define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */
|
||||
#define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
|
||||
#define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
|
||||
|
||||
#define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */
|
||||
#define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */
|
||||
#define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */
|
||||
|
||||
/*
|
||||
* Testchip peripheral and fpga gic regions
|
||||
*/
|
||||
#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
|
||||
#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
|
||||
#define REALVIEW_TC11MP_TWD_BASE 0x1F000700
|
||||
#define REALVIEW_TC11MP_TWD_SIZE 0x00000100
|
||||
#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
|
||||
#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
|
||||
|
||||
/*
|
||||
* Irqs
|
||||
*/
|
||||
#define IRQ_TC11MP_GIC_START 32
|
||||
#define IRQ_PB11MP_GIC_START 64
|
||||
|
||||
/*
|
||||
* ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
|
||||
*/
|
||||
#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0)
|
||||
#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1)
|
||||
#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2)
|
||||
#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3)
|
||||
#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4)
|
||||
#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5)
|
||||
#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6)
|
||||
#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7)
|
||||
#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8)
|
||||
#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9)
|
||||
#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */
|
||||
#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */
|
||||
#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */
|
||||
#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */
|
||||
#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14)
|
||||
#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15)
|
||||
|
||||
#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17)
|
||||
#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18)
|
||||
#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19)
|
||||
#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20)
|
||||
#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21)
|
||||
#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22)
|
||||
#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23)
|
||||
#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24)
|
||||
#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25)
|
||||
#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26)
|
||||
#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27)
|
||||
#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28)
|
||||
|
||||
#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29)
|
||||
#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30)
|
||||
#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31)
|
||||
|
||||
/*
|
||||
* RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
|
||||
*/
|
||||
#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */
|
||||
#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */
|
||||
#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */
|
||||
#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */
|
||||
#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */
|
||||
#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */
|
||||
#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */
|
||||
/* 9 reserved */
|
||||
#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */
|
||||
#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */
|
||||
#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */
|
||||
#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */
|
||||
#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */
|
||||
#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */
|
||||
#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */
|
||||
#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */
|
||||
#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */
|
||||
#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */
|
||||
#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */
|
||||
#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */
|
||||
#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */
|
||||
#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */
|
||||
#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */
|
||||
#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */
|
||||
#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */
|
||||
#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */
|
||||
#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */
|
||||
#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */
|
||||
#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */
|
||||
#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */
|
||||
|
||||
#define IRQ_PB11MP_SMC -1
|
||||
#define IRQ_PB11MP_SCTL -1
|
||||
|
||||
#define NR_GIC_PB11MP 2
|
||||
|
||||
/*
|
||||
* Only define NR_IRQS if less than NR_IRQS_PB11MP
|
||||
*/
|
||||
#define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96)
|
||||
|
||||
#if defined(CONFIG_MACH_REALVIEW_PB11MP)
|
||||
|
||||
#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
|
||||
#undef NR_IRQS
|
||||
#define NR_IRQS NR_IRQS_PB11MP
|
||||
#endif
|
||||
|
||||
#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
|
||||
#undef MAX_GIC_NR
|
||||
#define MAX_GIC_NR NR_GIC_PB11MP
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_MACH_REALVIEW_PB11MP */
|
||||
|
||||
#endif /* __ASM_ARCH_BOARD_PB11MP_H */
|
||||
|
|
@ -23,6 +23,7 @@
|
|||
#define __ASM_ARCH_IRQS_H
|
||||
|
||||
#include <asm/arch/board-eb.h>
|
||||
#include <asm/arch/board-pb11mp.h>
|
||||
|
||||
#define IRQ_LOCALTIMER 29
|
||||
#define IRQ_LOCALWDOG 30
|
||||
|
|
|
|||
Loading…
Reference in a new issue