sungem: Fix global namespace pollution of phy accessors.
The sungem driver has "phy_read()" and "phy_write()" functions, which we need to rename because the generic phy layer is about to export generic interfaces with the same name. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
73852b2bfb
commit
abc4da4503
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@ -115,7 +115,7 @@ static const struct pci_device_id gem_pci_tbl[] = {
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MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
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static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
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static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
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{
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u32 cmd;
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int limit = 10000;
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@ -141,18 +141,18 @@ static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
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return cmd & MIF_FRAME_DATA;
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}
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static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
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static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
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{
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struct gem *gp = netdev_priv(dev);
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return __phy_read(gp, mii_id, reg);
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return __sungem_phy_read(gp, mii_id, reg);
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}
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static inline u16 phy_read(struct gem *gp, int reg)
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static inline u16 sungem_phy_read(struct gem *gp, int reg)
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{
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return __phy_read(gp, gp->mii_phy_addr, reg);
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return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
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}
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static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
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static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
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{
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u32 cmd;
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int limit = 10000;
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@ -174,15 +174,15 @@ static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
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}
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}
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static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
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static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
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{
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struct gem *gp = netdev_priv(dev);
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__phy_write(gp, mii_id, reg, val & 0xffff);
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__sungem_phy_write(gp, mii_id, reg, val & 0xffff);
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}
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static inline void phy_write(struct gem *gp, int reg, u16 val)
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static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
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{
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__phy_write(gp, gp->mii_phy_addr, reg, val);
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__sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
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}
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static inline void gem_enable_ints(struct gem *gp)
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@ -1687,9 +1687,9 @@ static void gem_init_phy(struct gem *gp)
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/* Some PHYs used by apple have problem getting back to us,
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* we do an additional reset here
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*/
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phy_write(gp, MII_BMCR, BMCR_RESET);
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sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
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msleep(20);
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if (phy_read(gp, MII_BMCR) != 0xffff)
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if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
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break;
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if (i == 2)
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netdev_warn(gp->dev, "GMAC PHY not responding !\n");
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@ -2012,7 +2012,7 @@ static int gem_check_invariants(struct gem *gp)
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for (i = 0; i < 32; i++) {
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gp->mii_phy_addr = i;
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if (phy_read(gp, MII_BMCR) != 0xffff)
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if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
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break;
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}
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if (i == 32) {
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@ -2696,13 +2696,13 @@ static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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/* Fallthrough... */
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case SIOCGMIIREG: /* Read MII PHY register. */
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data->val_out = __phy_read(gp, data->phy_id & 0x1f,
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data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
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data->reg_num & 0x1f);
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rc = 0;
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break;
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case SIOCSMIIREG: /* Write MII PHY register. */
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__phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
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__sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
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data->val_in);
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rc = 0;
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break;
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@ -2933,8 +2933,8 @@ static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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/* Fill up the mii_phy structure (even if we won't use it) */
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gp->phy_mii.dev = dev;
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gp->phy_mii.mdio_read = _phy_read;
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gp->phy_mii.mdio_write = _phy_write;
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gp->phy_mii.mdio_read = _sungem_phy_read;
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gp->phy_mii.mdio_write = _sungem_phy_write;
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#ifdef CONFIG_PPC_PMAC
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gp->phy_mii.platform_data = gp->of_node;
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#endif
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@ -47,22 +47,22 @@ static const int phy_BCM5400_link_table[8][3] = {
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{ 1, 0, 1 }, /* 1000BT */
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};
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static inline int __phy_read(struct mii_phy* phy, int id, int reg)
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static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg)
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{
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return phy->mdio_read(phy->dev, id, reg);
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}
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static inline void __phy_write(struct mii_phy* phy, int id, int reg, int val)
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static inline void __sungem_phy_write(struct mii_phy* phy, int id, int reg, int val)
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{
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phy->mdio_write(phy->dev, id, reg, val);
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}
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static inline int phy_read(struct mii_phy* phy, int reg)
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static inline int sungem_phy_read(struct mii_phy* phy, int reg)
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{
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return phy->mdio_read(phy->dev, phy->mii_id, reg);
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}
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static inline void phy_write(struct mii_phy* phy, int reg, int val)
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static inline void sungem_phy_write(struct mii_phy* phy, int reg, int val)
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{
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phy->mdio_write(phy->dev, phy->mii_id, reg, val);
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}
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@ -72,21 +72,21 @@ static int reset_one_mii_phy(struct mii_phy* phy, int phy_id)
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u16 val;
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int limit = 10000;
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val = __phy_read(phy, phy_id, MII_BMCR);
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val = __sungem_phy_read(phy, phy_id, MII_BMCR);
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val &= ~(BMCR_ISOLATE | BMCR_PDOWN);
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val |= BMCR_RESET;
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__phy_write(phy, phy_id, MII_BMCR, val);
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__sungem_phy_write(phy, phy_id, MII_BMCR, val);
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udelay(100);
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while (--limit) {
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val = __phy_read(phy, phy_id, MII_BMCR);
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val = __sungem_phy_read(phy, phy_id, MII_BMCR);
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if ((val & BMCR_RESET) == 0)
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break;
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udelay(10);
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}
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if ((val & BMCR_ISOLATE) && limit > 0)
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__phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
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__sungem_phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
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return limit <= 0;
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}
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@ -95,19 +95,19 @@ static int bcm5201_init(struct mii_phy* phy)
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{
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u16 data;
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data = phy_read(phy, MII_BCM5201_MULTIPHY);
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data = sungem_phy_read(phy, MII_BCM5201_MULTIPHY);
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data &= ~MII_BCM5201_MULTIPHY_SUPERISOLATE;
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phy_write(phy, MII_BCM5201_MULTIPHY, data);
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sungem_phy_write(phy, MII_BCM5201_MULTIPHY, data);
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phy_write(phy, MII_BCM5201_INTERRUPT, 0);
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sungem_phy_write(phy, MII_BCM5201_INTERRUPT, 0);
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return 0;
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}
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static int bcm5201_suspend(struct mii_phy* phy)
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{
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phy_write(phy, MII_BCM5201_INTERRUPT, 0);
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phy_write(phy, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
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sungem_phy_write(phy, MII_BCM5201_INTERRUPT, 0);
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sungem_phy_write(phy, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
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return 0;
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}
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@ -116,20 +116,20 @@ static int bcm5221_init(struct mii_phy* phy)
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{
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u16 data;
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data = sungem_phy_read(phy, MII_BCM5221_TEST);
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sungem_phy_write(phy, MII_BCM5221_TEST,
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data | MII_BCM5221_TEST_ENABLE_SHADOWS);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
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data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
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sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
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data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data | MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR);
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data = sungem_phy_read(phy, MII_BCM5221_TEST);
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sungem_phy_write(phy, MII_BCM5221_TEST,
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data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
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return 0;
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@ -139,12 +139,12 @@ static int bcm5221_suspend(struct mii_phy* phy)
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{
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u16 data;
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data = sungem_phy_read(phy, MII_BCM5221_TEST);
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sungem_phy_write(phy, MII_BCM5221_TEST,
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data | MII_BCM5221_TEST_ENABLE_SHADOWS);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data | MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE);
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return 0;
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@ -154,20 +154,20 @@ static int bcm5241_init(struct mii_phy* phy)
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{
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u16 data;
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data = sungem_phy_read(phy, MII_BCM5221_TEST);
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sungem_phy_write(phy, MII_BCM5221_TEST,
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data | MII_BCM5221_TEST_ENABLE_SHADOWS);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
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data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
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sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
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data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data & ~MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data = sungem_phy_read(phy, MII_BCM5221_TEST);
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sungem_phy_write(phy, MII_BCM5221_TEST,
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data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
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return 0;
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@ -177,12 +177,12 @@ static int bcm5241_suspend(struct mii_phy* phy)
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{
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u16 data;
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data = sungem_phy_read(phy, MII_BCM5221_TEST);
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sungem_phy_write(phy, MII_BCM5221_TEST,
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data | MII_BCM5221_TEST_ENABLE_SHADOWS);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data | MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
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return 0;
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@ -193,26 +193,26 @@ static int bcm5400_init(struct mii_phy* phy)
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u16 data;
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/* Configure for gigabit full duplex */
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data = phy_read(phy, MII_BCM5400_AUXCONTROL);
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data = sungem_phy_read(phy, MII_BCM5400_AUXCONTROL);
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data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
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phy_write(phy, MII_BCM5400_AUXCONTROL, data);
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sungem_phy_write(phy, MII_BCM5400_AUXCONTROL, data);
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data = phy_read(phy, MII_BCM5400_GB_CONTROL);
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data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
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data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
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phy_write(phy, MII_BCM5400_GB_CONTROL, data);
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sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
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udelay(100);
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/* Reset and configure cascaded 10/100 PHY */
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(void)reset_one_mii_phy(phy, 0x1f);
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data = __phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
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data = __sungem_phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
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data |= MII_BCM5201_MULTIPHY_SERIALMODE;
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__phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
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__sungem_phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
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data = phy_read(phy, MII_BCM5400_AUXCONTROL);
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data = sungem_phy_read(phy, MII_BCM5400_AUXCONTROL);
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data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
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phy_write(phy, MII_BCM5400_AUXCONTROL, data);
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sungem_phy_write(phy, MII_BCM5400_AUXCONTROL, data);
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return 0;
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}
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@ -220,7 +220,7 @@ static int bcm5400_init(struct mii_phy* phy)
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static int bcm5400_suspend(struct mii_phy* phy)
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{
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#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
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phy_write(phy, MII_BMCR, BMCR_PDOWN);
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sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
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#endif
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return 0;
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}
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@ -230,7 +230,7 @@ static int bcm5401_init(struct mii_phy* phy)
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u16 data;
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int rev;
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rev = phy_read(phy, MII_PHYSID2) & 0x000f;
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rev = sungem_phy_read(phy, MII_PHYSID2) & 0x000f;
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if (rev == 0 || rev == 3) {
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/* Some revisions of 5401 appear to need this
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* initialisation sequence to disable, according
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@ -243,32 +243,32 @@ static int bcm5401_init(struct mii_phy* phy)
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* Note: This should (and does) match tg3_init_5401phy_dsp
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* in the tg3.c driver. -DaveM
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*/
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phy_write(phy, 0x18, 0x0c20);
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phy_write(phy, 0x17, 0x0012);
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phy_write(phy, 0x15, 0x1804);
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phy_write(phy, 0x17, 0x0013);
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phy_write(phy, 0x15, 0x1204);
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phy_write(phy, 0x17, 0x8006);
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phy_write(phy, 0x15, 0x0132);
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phy_write(phy, 0x17, 0x8006);
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phy_write(phy, 0x15, 0x0232);
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phy_write(phy, 0x17, 0x201f);
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phy_write(phy, 0x15, 0x0a20);
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sungem_phy_write(phy, 0x18, 0x0c20);
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sungem_phy_write(phy, 0x17, 0x0012);
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sungem_phy_write(phy, 0x15, 0x1804);
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sungem_phy_write(phy, 0x17, 0x0013);
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sungem_phy_write(phy, 0x15, 0x1204);
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sungem_phy_write(phy, 0x17, 0x8006);
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sungem_phy_write(phy, 0x15, 0x0132);
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sungem_phy_write(phy, 0x17, 0x8006);
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sungem_phy_write(phy, 0x15, 0x0232);
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sungem_phy_write(phy, 0x17, 0x201f);
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sungem_phy_write(phy, 0x15, 0x0a20);
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}
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/* Configure for gigabit full duplex */
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data = phy_read(phy, MII_BCM5400_GB_CONTROL);
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data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
|
||||
data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
|
||||
phy_write(phy, MII_BCM5400_GB_CONTROL, data);
|
||||
sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
|
||||
|
||||
udelay(10);
|
||||
|
||||
/* Reset and configure cascaded 10/100 PHY */
|
||||
(void)reset_one_mii_phy(phy, 0x1f);
|
||||
|
||||
data = __phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
|
||||
data = __sungem_phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
|
||||
data |= MII_BCM5201_MULTIPHY_SERIALMODE;
|
||||
__phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
|
||||
__sungem_phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -276,7 +276,7 @@ static int bcm5401_init(struct mii_phy* phy)
|
|||
static int bcm5401_suspend(struct mii_phy* phy)
|
||||
{
|
||||
#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
|
||||
phy_write(phy, MII_BMCR, BMCR_PDOWN);
|
||||
sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
@ -288,19 +288,19 @@ static int bcm5411_init(struct mii_phy* phy)
|
|||
/* Here's some more Apple black magic to setup
|
||||
* some voltage stuffs.
|
||||
*/
|
||||
phy_write(phy, 0x1c, 0x8c23);
|
||||
phy_write(phy, 0x1c, 0x8ca3);
|
||||
phy_write(phy, 0x1c, 0x8c23);
|
||||
sungem_phy_write(phy, 0x1c, 0x8c23);
|
||||
sungem_phy_write(phy, 0x1c, 0x8ca3);
|
||||
sungem_phy_write(phy, 0x1c, 0x8c23);
|
||||
|
||||
/* Here, Apple seems to want to reset it, do
|
||||
* it as well
|
||||
*/
|
||||
phy_write(phy, MII_BMCR, BMCR_RESET);
|
||||
phy_write(phy, MII_BMCR, 0x1340);
|
||||
sungem_phy_write(phy, MII_BMCR, BMCR_RESET);
|
||||
sungem_phy_write(phy, MII_BMCR, 0x1340);
|
||||
|
||||
data = phy_read(phy, MII_BCM5400_GB_CONTROL);
|
||||
data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
|
||||
data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
|
||||
phy_write(phy, MII_BCM5400_GB_CONTROL, data);
|
||||
sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
|
||||
|
||||
udelay(10);
|
||||
|
||||
|
@ -321,7 +321,7 @@ static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
|
|||
phy->advertising = advertise;
|
||||
|
||||
/* Setup standard advertise */
|
||||
adv = phy_read(phy, MII_ADVERTISE);
|
||||
adv = sungem_phy_read(phy, MII_ADVERTISE);
|
||||
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
|
||||
if (advertise & ADVERTISED_10baseT_Half)
|
||||
adv |= ADVERTISE_10HALF;
|
||||
|
@ -331,12 +331,12 @@ static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
|
|||
adv |= ADVERTISE_100HALF;
|
||||
if (advertise & ADVERTISED_100baseT_Full)
|
||||
adv |= ADVERTISE_100FULL;
|
||||
phy_write(phy, MII_ADVERTISE, adv);
|
||||
sungem_phy_write(phy, MII_ADVERTISE, adv);
|
||||
|
||||
/* Start/Restart aneg */
|
||||
ctl = phy_read(phy, MII_BMCR);
|
||||
ctl = sungem_phy_read(phy, MII_BMCR);
|
||||
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
|
||||
phy_write(phy, MII_BMCR, ctl);
|
||||
sungem_phy_write(phy, MII_BMCR, ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -350,11 +350,11 @@ static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
|
|||
phy->duplex = fd;
|
||||
phy->pause = 0;
|
||||
|
||||
ctl = phy_read(phy, MII_BMCR);
|
||||
ctl = sungem_phy_read(phy, MII_BMCR);
|
||||
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE);
|
||||
|
||||
/* First reset the PHY */
|
||||
phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
|
||||
sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
|
||||
|
||||
/* Select speed & duplex */
|
||||
switch(speed) {
|
||||
|
@ -369,7 +369,7 @@ static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
|
|||
}
|
||||
if (fd == DUPLEX_FULL)
|
||||
ctl |= BMCR_FULLDPLX;
|
||||
phy_write(phy, MII_BMCR, ctl);
|
||||
sungem_phy_write(phy, MII_BMCR, ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -378,8 +378,8 @@ static int genmii_poll_link(struct mii_phy *phy)
|
|||
{
|
||||
u16 status;
|
||||
|
||||
(void)phy_read(phy, MII_BMSR);
|
||||
status = phy_read(phy, MII_BMSR);
|
||||
(void)sungem_phy_read(phy, MII_BMSR);
|
||||
status = sungem_phy_read(phy, MII_BMSR);
|
||||
if ((status & BMSR_LSTATUS) == 0)
|
||||
return 0;
|
||||
if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE))
|
||||
|
@ -392,7 +392,7 @@ static int genmii_read_link(struct mii_phy *phy)
|
|||
u16 lpa;
|
||||
|
||||
if (phy->autoneg) {
|
||||
lpa = phy_read(phy, MII_LPA);
|
||||
lpa = sungem_phy_read(phy, MII_LPA);
|
||||
|
||||
if (lpa & (LPA_10FULL | LPA_100FULL))
|
||||
phy->duplex = DUPLEX_FULL;
|
||||
|
@ -413,7 +413,7 @@ static int genmii_read_link(struct mii_phy *phy)
|
|||
|
||||
static int generic_suspend(struct mii_phy* phy)
|
||||
{
|
||||
phy_write(phy, MII_BMCR, BMCR_PDOWN);
|
||||
sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -423,27 +423,27 @@ static int bcm5421_init(struct mii_phy* phy)
|
|||
u16 data;
|
||||
unsigned int id;
|
||||
|
||||
id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2));
|
||||
id = (sungem_phy_read(phy, MII_PHYSID1) << 16 | sungem_phy_read(phy, MII_PHYSID2));
|
||||
|
||||
/* Revision 0 of 5421 needs some fixups */
|
||||
if (id == 0x002060e0) {
|
||||
/* This is borrowed from MacOS
|
||||
*/
|
||||
phy_write(phy, 0x18, 0x1007);
|
||||
data = phy_read(phy, 0x18);
|
||||
phy_write(phy, 0x18, data | 0x0400);
|
||||
phy_write(phy, 0x18, 0x0007);
|
||||
data = phy_read(phy, 0x18);
|
||||
phy_write(phy, 0x18, data | 0x0800);
|
||||
phy_write(phy, 0x17, 0x000a);
|
||||
data = phy_read(phy, 0x15);
|
||||
phy_write(phy, 0x15, data | 0x0200);
|
||||
sungem_phy_write(phy, 0x18, 0x1007);
|
||||
data = sungem_phy_read(phy, 0x18);
|
||||
sungem_phy_write(phy, 0x18, data | 0x0400);
|
||||
sungem_phy_write(phy, 0x18, 0x0007);
|
||||
data = sungem_phy_read(phy, 0x18);
|
||||
sungem_phy_write(phy, 0x18, data | 0x0800);
|
||||
sungem_phy_write(phy, 0x17, 0x000a);
|
||||
data = sungem_phy_read(phy, 0x15);
|
||||
sungem_phy_write(phy, 0x15, data | 0x0200);
|
||||
}
|
||||
|
||||
/* Pick up some init code from OF for K2 version */
|
||||
if ((id & 0xfffffff0) == 0x002062e0) {
|
||||
phy_write(phy, 4, 0x01e1);
|
||||
phy_write(phy, 9, 0x0300);
|
||||
sungem_phy_write(phy, 4, 0x01e1);
|
||||
sungem_phy_write(phy, 9, 0x0300);
|
||||
}
|
||||
|
||||
/* Check if we can enable automatic low power */
|
||||
|
@ -455,9 +455,9 @@ static int bcm5421_init(struct mii_phy* phy)
|
|||
can_low_power = 0;
|
||||
if (can_low_power) {
|
||||
/* Enable automatic low-power */
|
||||
phy_write(phy, 0x1c, 0x9002);
|
||||
phy_write(phy, 0x1c, 0xa821);
|
||||
phy_write(phy, 0x1c, 0x941d);
|
||||
sungem_phy_write(phy, 0x1c, 0x9002);
|
||||
sungem_phy_write(phy, 0x1c, 0xa821);
|
||||
sungem_phy_write(phy, 0x1c, 0x941d);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_PPC_PMAC */
|
||||
|
@ -476,7 +476,7 @@ static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
|
|||
phy->advertising = advertise;
|
||||
|
||||
/* Setup standard advertise */
|
||||
adv = phy_read(phy, MII_ADVERTISE);
|
||||
adv = sungem_phy_read(phy, MII_ADVERTISE);
|
||||
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
|
||||
if (advertise & ADVERTISED_10baseT_Half)
|
||||
adv |= ADVERTISE_10HALF;
|
||||
|
@ -490,21 +490,21 @@ static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
|
|||
adv |= ADVERTISE_PAUSE_CAP;
|
||||
if (advertise & ADVERTISED_Asym_Pause)
|
||||
adv |= ADVERTISE_PAUSE_ASYM;
|
||||
phy_write(phy, MII_ADVERTISE, adv);
|
||||
sungem_phy_write(phy, MII_ADVERTISE, adv);
|
||||
|
||||
/* Setup 1000BT advertise */
|
||||
adv = phy_read(phy, MII_1000BASETCONTROL);
|
||||
adv = sungem_phy_read(phy, MII_1000BASETCONTROL);
|
||||
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP|MII_1000BASETCONTROL_HALFDUPLEXCAP);
|
||||
if (advertise & SUPPORTED_1000baseT_Half)
|
||||
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
|
||||
if (advertise & SUPPORTED_1000baseT_Full)
|
||||
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
|
||||
phy_write(phy, MII_1000BASETCONTROL, adv);
|
||||
sungem_phy_write(phy, MII_1000BASETCONTROL, adv);
|
||||
|
||||
/* Start/Restart aneg */
|
||||
ctl = phy_read(phy, MII_BMCR);
|
||||
ctl = sungem_phy_read(phy, MII_BMCR);
|
||||
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
|
||||
phy_write(phy, MII_BMCR, ctl);
|
||||
sungem_phy_write(phy, MII_BMCR, ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -518,11 +518,11 @@ static int bcm54xx_setup_forced(struct mii_phy *phy, int speed, int fd)
|
|||
phy->duplex = fd;
|
||||
phy->pause = 0;
|
||||
|
||||
ctl = phy_read(phy, MII_BMCR);
|
||||
ctl = sungem_phy_read(phy, MII_BMCR);
|
||||
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
|
||||
|
||||
/* First reset the PHY */
|
||||
phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
|
||||
sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
|
||||
|
||||
/* Select speed & duplex */
|
||||
switch(speed) {
|
||||
|
@ -539,7 +539,7 @@ static int bcm54xx_setup_forced(struct mii_phy *phy, int speed, int fd)
|
|||
|
||||
// XXX Should we set the sungem to GII now on 1000BT ?
|
||||
|
||||
phy_write(phy, MII_BMCR, ctl);
|
||||
sungem_phy_write(phy, MII_BMCR, ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -550,7 +550,7 @@ static int bcm54xx_read_link(struct mii_phy *phy)
|
|||
u16 val;
|
||||
|
||||
if (phy->autoneg) {
|
||||
val = phy_read(phy, MII_BCM5400_AUXSTATUS);
|
||||
val = sungem_phy_read(phy, MII_BCM5400_AUXSTATUS);
|
||||
link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
|
||||
MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT);
|
||||
phy->duplex = phy_BCM5400_link_table[link_mode][0] ?
|
||||
|
@ -559,7 +559,7 @@ static int bcm54xx_read_link(struct mii_phy *phy)
|
|||
SPEED_1000 :
|
||||
(phy_BCM5400_link_table[link_mode][1] ?
|
||||
SPEED_100 : SPEED_10);
|
||||
val = phy_read(phy, MII_LPA);
|
||||
val = sungem_phy_read(phy, MII_LPA);
|
||||
phy->pause = (phy->duplex == DUPLEX_FULL) &&
|
||||
((val & LPA_PAUSE) != 0);
|
||||
}
|
||||
|
@ -575,19 +575,19 @@ static int marvell88e1111_init(struct mii_phy* phy)
|
|||
u16 rev;
|
||||
|
||||
/* magic init sequence for rev 0 */
|
||||
rev = phy_read(phy, MII_PHYSID2) & 0x000f;
|
||||
rev = sungem_phy_read(phy, MII_PHYSID2) & 0x000f;
|
||||
if (rev == 0) {
|
||||
phy_write(phy, 0x1d, 0x000a);
|
||||
phy_write(phy, 0x1e, 0x0821);
|
||||
sungem_phy_write(phy, 0x1d, 0x000a);
|
||||
sungem_phy_write(phy, 0x1e, 0x0821);
|
||||
|
||||
phy_write(phy, 0x1d, 0x0006);
|
||||
phy_write(phy, 0x1e, 0x8600);
|
||||
sungem_phy_write(phy, 0x1d, 0x0006);
|
||||
sungem_phy_write(phy, 0x1e, 0x8600);
|
||||
|
||||
phy_write(phy, 0x1d, 0x000b);
|
||||
phy_write(phy, 0x1e, 0x0100);
|
||||
sungem_phy_write(phy, 0x1d, 0x000b);
|
||||
sungem_phy_write(phy, 0x1e, 0x0100);
|
||||
|
||||
phy_write(phy, 0x1d, 0x0004);
|
||||
phy_write(phy, 0x1e, 0x4850);
|
||||
sungem_phy_write(phy, 0x1d, 0x0004);
|
||||
sungem_phy_write(phy, 0x1e, 0x4850);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
@ -600,8 +600,8 @@ static int bcm5421_poll_link(struct mii_phy* phy)
|
|||
int mode;
|
||||
|
||||
/* find out in what mode we are */
|
||||
phy_write(phy, MII_NCONFIG, 0x1000);
|
||||
phy_reg = phy_read(phy, MII_NCONFIG);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x1000);
|
||||
phy_reg = sungem_phy_read(phy, MII_NCONFIG);
|
||||
|
||||
mode = (phy_reg & BCM5421_MODE_MASK) >> 5;
|
||||
|
||||
|
@ -609,8 +609,8 @@ static int bcm5421_poll_link(struct mii_phy* phy)
|
|||
return genmii_poll_link(phy);
|
||||
|
||||
/* try to find out whether we have a link */
|
||||
phy_write(phy, MII_NCONFIG, 0x2000);
|
||||
phy_reg = phy_read(phy, MII_NCONFIG);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x2000);
|
||||
phy_reg = sungem_phy_read(phy, MII_NCONFIG);
|
||||
|
||||
if (phy_reg & 0x0020)
|
||||
return 0;
|
||||
|
@ -624,8 +624,8 @@ static int bcm5421_read_link(struct mii_phy* phy)
|
|||
int mode;
|
||||
|
||||
/* find out in what mode we are */
|
||||
phy_write(phy, MII_NCONFIG, 0x1000);
|
||||
phy_reg = phy_read(phy, MII_NCONFIG);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x1000);
|
||||
phy_reg = sungem_phy_read(phy, MII_NCONFIG);
|
||||
|
||||
mode = (phy_reg & BCM5421_MODE_MASK ) >> 5;
|
||||
|
||||
|
@ -635,8 +635,8 @@ static int bcm5421_read_link(struct mii_phy* phy)
|
|||
phy->speed = SPEED_1000;
|
||||
|
||||
/* find out whether we are running half- or full duplex */
|
||||
phy_write(phy, MII_NCONFIG, 0x2000);
|
||||
phy_reg = phy_read(phy, MII_NCONFIG);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x2000);
|
||||
phy_reg = sungem_phy_read(phy, MII_NCONFIG);
|
||||
|
||||
if ( (phy_reg & 0x0080) >> 7)
|
||||
phy->duplex |= DUPLEX_HALF;
|
||||
|
@ -649,14 +649,14 @@ static int bcm5421_read_link(struct mii_phy* phy)
|
|||
static int bcm5421_enable_fiber(struct mii_phy* phy, int autoneg)
|
||||
{
|
||||
/* enable fiber mode */
|
||||
phy_write(phy, MII_NCONFIG, 0x9020);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x9020);
|
||||
/* LEDs active in both modes, autosense prio = fiber */
|
||||
phy_write(phy, MII_NCONFIG, 0x945f);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x945f);
|
||||
|
||||
if (!autoneg) {
|
||||
/* switch off fibre autoneg */
|
||||
phy_write(phy, MII_NCONFIG, 0xfc01);
|
||||
phy_write(phy, 0x0b, 0x0004);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0xfc01);
|
||||
sungem_phy_write(phy, 0x0b, 0x0004);
|
||||
}
|
||||
|
||||
phy->autoneg = autoneg;
|
||||
|
@ -673,8 +673,8 @@ static int bcm5461_poll_link(struct mii_phy* phy)
|
|||
int mode;
|
||||
|
||||
/* find out in what mode we are */
|
||||
phy_write(phy, MII_NCONFIG, 0x7c00);
|
||||
phy_reg = phy_read(phy, MII_NCONFIG);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x7c00);
|
||||
phy_reg = sungem_phy_read(phy, MII_NCONFIG);
|
||||
|
||||
mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
|
||||
|
||||
|
@ -682,8 +682,8 @@ static int bcm5461_poll_link(struct mii_phy* phy)
|
|||
return genmii_poll_link(phy);
|
||||
|
||||
/* find out whether we have a link */
|
||||
phy_write(phy, MII_NCONFIG, 0x7000);
|
||||
phy_reg = phy_read(phy, MII_NCONFIG);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x7000);
|
||||
phy_reg = sungem_phy_read(phy, MII_NCONFIG);
|
||||
|
||||
if (phy_reg & BCM5461_FIBER_LINK)
|
||||
return 1;
|
||||
|
@ -699,8 +699,8 @@ static int bcm5461_read_link(struct mii_phy* phy)
|
|||
int mode;
|
||||
|
||||
/* find out in what mode we are */
|
||||
phy_write(phy, MII_NCONFIG, 0x7c00);
|
||||
phy_reg = phy_read(phy, MII_NCONFIG);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x7c00);
|
||||
phy_reg = sungem_phy_read(phy, MII_NCONFIG);
|
||||
|
||||
mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
|
||||
|
||||
|
@ -711,8 +711,8 @@ static int bcm5461_read_link(struct mii_phy* phy)
|
|||
phy->speed = SPEED_1000;
|
||||
|
||||
/* find out whether we are running half- or full duplex */
|
||||
phy_write(phy, MII_NCONFIG, 0x7000);
|
||||
phy_reg = phy_read(phy, MII_NCONFIG);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0x7000);
|
||||
phy_reg = sungem_phy_read(phy, MII_NCONFIG);
|
||||
|
||||
if (phy_reg & BCM5461_FIBER_DUPLEX)
|
||||
phy->duplex |= DUPLEX_FULL;
|
||||
|
@ -725,15 +725,15 @@ static int bcm5461_read_link(struct mii_phy* phy)
|
|||
static int bcm5461_enable_fiber(struct mii_phy* phy, int autoneg)
|
||||
{
|
||||
/* select fiber mode, enable 1000 base-X registers */
|
||||
phy_write(phy, MII_NCONFIG, 0xfc0b);
|
||||
sungem_phy_write(phy, MII_NCONFIG, 0xfc0b);
|
||||
|
||||
if (autoneg) {
|
||||
/* enable fiber with no autonegotiation */
|
||||
phy_write(phy, MII_ADVERTISE, 0x01e0);
|
||||
phy_write(phy, MII_BMCR, 0x1140);
|
||||
sungem_phy_write(phy, MII_ADVERTISE, 0x01e0);
|
||||
sungem_phy_write(phy, MII_BMCR, 0x1140);
|
||||
} else {
|
||||
/* enable fiber with autonegotiation */
|
||||
phy_write(phy, MII_BMCR, 0x0140);
|
||||
sungem_phy_write(phy, MII_BMCR, 0x0140);
|
||||
}
|
||||
|
||||
phy->autoneg = autoneg;
|
||||
|
@ -752,7 +752,7 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
|
|||
phy->advertising = advertise;
|
||||
|
||||
/* Setup standard advertise */
|
||||
adv = phy_read(phy, MII_ADVERTISE);
|
||||
adv = sungem_phy_read(phy, MII_ADVERTISE);
|
||||
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
|
||||
if (advertise & ADVERTISED_10baseT_Half)
|
||||
adv |= ADVERTISE_10HALF;
|
||||
|
@ -766,7 +766,7 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
|
|||
adv |= ADVERTISE_PAUSE_CAP;
|
||||
if (advertise & ADVERTISED_Asym_Pause)
|
||||
adv |= ADVERTISE_PAUSE_ASYM;
|
||||
phy_write(phy, MII_ADVERTISE, adv);
|
||||
sungem_phy_write(phy, MII_ADVERTISE, adv);
|
||||
|
||||
/* Setup 1000BT advertise & enable crossover detect
|
||||
* XXX How do we advertise 1000BT ? Darwin source is
|
||||
|
@ -774,7 +774,7 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
|
|||
* write to control... Someone has specs for those
|
||||
* beasts ?
|
||||
*/
|
||||
adv = phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
|
||||
adv = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
|
||||
adv |= MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX;
|
||||
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
|
||||
MII_1000BASETCONTROL_HALFDUPLEXCAP);
|
||||
|
@ -782,12 +782,12 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
|
|||
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
|
||||
if (advertise & SUPPORTED_1000baseT_Full)
|
||||
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
|
||||
phy_write(phy, MII_1000BASETCONTROL, adv);
|
||||
sungem_phy_write(phy, MII_1000BASETCONTROL, adv);
|
||||
|
||||
/* Start/Restart aneg */
|
||||
ctl = phy_read(phy, MII_BMCR);
|
||||
ctl = sungem_phy_read(phy, MII_BMCR);
|
||||
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
|
||||
phy_write(phy, MII_BMCR, ctl);
|
||||
sungem_phy_write(phy, MII_BMCR, ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -801,7 +801,7 @@ static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
|
|||
phy->duplex = fd;
|
||||
phy->pause = 0;
|
||||
|
||||
ctl = phy_read(phy, MII_BMCR);
|
||||
ctl = sungem_phy_read(phy, MII_BMCR);
|
||||
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
|
||||
ctl |= BMCR_RESET;
|
||||
|
||||
|
@ -824,7 +824,7 @@ static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
|
|||
/* Disable crossover. Again, the way Apple does it is strange,
|
||||
* though I don't assume they are wrong ;)
|
||||
*/
|
||||
ctl2 = phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
|
||||
ctl2 = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
|
||||
ctl2 &= ~(MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX |
|
||||
MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX |
|
||||
MII_1000BASETCONTROL_FULLDUPLEXCAP |
|
||||
|
@ -833,11 +833,11 @@ static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
|
|||
ctl2 |= (fd == DUPLEX_FULL) ?
|
||||
MII_1000BASETCONTROL_FULLDUPLEXCAP :
|
||||
MII_1000BASETCONTROL_HALFDUPLEXCAP;
|
||||
phy_write(phy, MII_1000BASETCONTROL, ctl2);
|
||||
sungem_phy_write(phy, MII_1000BASETCONTROL, ctl2);
|
||||
|
||||
// XXX Should we set the sungem to GII now on 1000BT ?
|
||||
|
||||
phy_write(phy, MII_BMCR, ctl);
|
||||
sungem_phy_write(phy, MII_BMCR, ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -847,7 +847,7 @@ static int marvell_read_link(struct mii_phy *phy)
|
|||
u16 status, pmask;
|
||||
|
||||
if (phy->autoneg) {
|
||||
status = phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
|
||||
status = sungem_phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
|
||||
if ((status & MII_M1011_PHY_SPEC_STATUS_RESOLVED) == 0)
|
||||
return -EAGAIN;
|
||||
if (status & MII_M1011_PHY_SPEC_STATUS_1000)
|
||||
|
@ -1174,7 +1174,7 @@ int sungem_phy_probe(struct mii_phy *phy, int mii_id)
|
|||
goto fail;
|
||||
|
||||
/* Read ID and find matching entry */
|
||||
id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2));
|
||||
id = (sungem_phy_read(phy, MII_PHYSID1) << 16 | sungem_phy_read(phy, MII_PHYSID2));
|
||||
printk(KERN_DEBUG KBUILD_MODNAME ": " "PHY ID: %x, addr: %x\n",
|
||||
id, mii_id);
|
||||
for (i=0; (def = mii_phy_table[i]) != NULL; i++)
|
||||
|
|
Loading…
Reference in a new issue