[WATCHDOG] i6300.h-removal-patch
the attached patch moves the content of drivers/char/watchdog/i6300.h into drivers/char/watchdog/i6300.c, since it is the only file using the defines there is no real reason to have a separate header. Also cleaned up the comments a bit and added myself to the copyright holders. Signed-off-by: David Hardeman <david@2gen.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> Signed-off-by: Andrew Morton <akpm@osdl.org>
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@ -1,20 +1,15 @@
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/*
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* i6300esb 0.03: Watchdog timer driver for Intel 6300ESB chipset
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* i6300esb: Watchdog timer driver for Intel 6300ESB chipset
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*
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* (c) Copyright 2004 Google Inc.
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* (c) Copyright 2005 David Härdeman <david@2gen.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* based on i810-tco.c which is
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*
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* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>
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* developed for
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* Jentro AG, Haar/Munich (Germany)
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*
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* which is in turn based on softdog.c by Alan Cox <alan@redhat.com>
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* based on i810-tco.c which is in turn based on softdog.c
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*
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* The timer is implemented in the following I/O controller hubs:
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* (See the intel documentation on http://developer.intel.com.)
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include "i6300esb.h"
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/* Module and version information */
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#define ESB_VERSION "0.03"
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#define ESB_MODULE_NAME "i6300ESB timer"
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#define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION
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#define PFX ESB_MODULE_NAME ": "
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/* PCI configuration registers */
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#define ESB_CONFIG_REG 0x60 /* Config register */
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#define ESB_LOCK_REG 0x68 /* WDT lock register */
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/* Memory mapped registers */
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#define ESB_TIMER1_REG BASEADDR + 0x00 /* Timer1 value after each reset */
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#define ESB_TIMER2_REG BASEADDR + 0x04 /* Timer2 value after each reset */
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#define ESB_GINTSR_REG BASEADDR + 0x08 /* General Interrupt Status Register */
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#define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */
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/* Lock register bits */
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#define ESB_WDT_FUNC ( 0x01 << 2 ) /* Watchdog functionality */
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#define ESB_WDT_ENABLE ( 0x01 << 1 ) /* Enable WDT */
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#define ESB_WDT_LOCK ( 0x01 << 0 ) /* Lock (nowayout) */
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/* Config register bits */
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#define ESB_WDT_REBOOT ( 0x01 << 5 ) /* Enable reboot on timeout */
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#define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */
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#define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */
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/* Reload register bits */
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#define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */
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/* Magic constants */
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#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
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#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
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/* internal variables */
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static void __iomem *BASEADDR;
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static spinlock_t esb_lock; /* Guards the hardware */
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/*
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* i6300esb: Watchdog timer driver for Intel 6300ESB chipset
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*
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* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights Reserved.
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* http://www.kernelconcepts.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Neither kernel concepts nor Nils Faerber admit liability nor provide
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* warranty for any of this software. This material is provided
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* "AS-IS" and at no charge.
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*
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* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>
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* developed for
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* Jentro AG, Haar/Munich (Germany)
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*
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* TCO timer driver for i8xx chipsets
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* based on softdog.c by Alan Cox <alan@redhat.com>
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*
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* For history and the complete list of supported I/O Controller Hub's
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* see i8xx_tco.c
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*/
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/*
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* Some address definitions for the TCO
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*/
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/* PCI configuration registers */
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#define ESB_CONFIG_REG 0x60 /* Config register */
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#define ESB_LOCK_REG 0x68 /* WDT lock register */
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/* Memory mapped registers */
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#define ESB_TIMER1_REG BASEADDR + 0x00 /* Timer1 value after each reset */
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#define ESB_TIMER2_REG BASEADDR + 0x04 /* Timer2 value after each reset */
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#define ESB_GINTSR_REG BASEADDR + 0x08 /* General Interrupt Status Register */
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#define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */
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/*
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* Some register bits
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*/
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/* Lock register bits */
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#define ESB_WDT_FUNC ( 0x01 << 2 ) /* Watchdog functionality */
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#define ESB_WDT_ENABLE ( 0x01 << 1 ) /* Enable WDT */
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#define ESB_WDT_LOCK ( 0x01 << 0 ) /* Lock (nowayout) */
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/* Config register bits */
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#define ESB_WDT_REBOOT ( 0x01 << 5 ) /* Enable reboot on timeout */
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#define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */
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#define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */
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/* Reload register bits */
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#define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */
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/*
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* Some magic constants
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*/
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#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
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#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
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