tile: do less L1 I-cache eviction
We had been doing an automatic full eviction of the L1 I$ everywhere whenever we did a kernel-space TLB flush. It turns out this isn't necessary, since all the callers already handle doing a flush if necessary. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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@ -91,8 +91,14 @@ void flush_tlb_all(void)
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}
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}
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/*
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* Callers need to flush the L1I themselves if necessary, e.g. for
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* kernel module unload. Otherwise we assume callers are not using
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* executable pgprot_t's. Using EVICT_L1I means that dataplane cpus
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* will get an unnecessary interrupt otherwise.
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*/
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
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flush_remote(0, 0, NULL,
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start, end - start, PAGE_SIZE, cpu_online_mask, NULL, 0);
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}
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