nvidiafb: Add proper support for Geforce 7600 chipset
Add proper support for the Geforce 7600 (device id 0x039x). This also sync's nvidiafb with the latest Xorg nv driver. Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -150,8 +150,7 @@ static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
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M = pll & 0xFF;
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N = (pll >> 8) & 0xFF;
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if (((par->Chipset & 0xfff0) == 0x0290) ||
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((par->Chipset & 0xfff0) == 0x0390) ||
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((par->Chipset & 0xfff0) == 0x02E0)) {
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((par->Chipset & 0xfff0) == 0x0390)) {
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MB = 1;
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NB = 1;
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} else {
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@ -161,7 +160,7 @@ static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
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*MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
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pll = NV_RD32(par->PMC, 0x4000);
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P = (pll >> 16) & 0x03;
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P = (pll >> 16) & 0x07;
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pll = NV_RD32(par->PMC, 0x4004);
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M = pll & 0xFF;
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N = (pll >> 8) & 0xFF;
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@ -892,11 +891,17 @@ void NVCalcStateExt(struct nvidia_par *par,
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state->general = bpp == 16 ? 0x00101100 : 0x00100100;
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state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
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break;
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case NV_ARCH_40:
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if (!par->FlatPanel)
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state->control = NV_RD32(par->PRAMDAC0, 0x0580) &
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0xeffffeff;
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/* fallthrough */
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case NV_ARCH_10:
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case NV_ARCH_20:
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case NV_ARCH_30:
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default:
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if ((par->Chipset & 0xfff0) == 0x0240) {
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if ((par->Chipset & 0xfff0) == 0x0240 ||
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(par->Chipset & 0xfff0) == 0x03d0) {
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state->arbitration0 = 256;
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state->arbitration1 = 0x0480;
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} else if (((par->Chipset & 0xffff) == 0x01A0) ||
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@ -939,7 +944,7 @@ void NVCalcStateExt(struct nvidia_par *par,
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void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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{
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int i;
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int i, j;
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NV_WR32(par->PMC, 0x0140, 0x00000000);
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NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
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@ -951,7 +956,8 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
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if (par->Architecture == NV_ARCH_04) {
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NV_WR32(par->PFB, 0x0200, state->config);
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if (state)
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NV_WR32(par->PFB, 0x0200, state->config);
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} else if ((par->Architecture < NV_ARCH_40) ||
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(par->Chipset & 0xfff0) == 0x0040) {
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for (i = 0; i < 8; i++) {
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@ -964,8 +970,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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if (((par->Chipset & 0xfff0) == 0x0090) ||
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((par->Chipset & 0xfff0) == 0x01D0) ||
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((par->Chipset & 0xfff0) == 0x02E0) ||
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((par->Chipset & 0xfff0) == 0x0290))
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((par->Chipset & 0xfff0) == 0x0290) ||
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((par->Chipset & 0xfff0) == 0x0390) ||
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((par->Chipset & 0xfff0) == 0x03D0))
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regions = 15;
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for(i = 0; i < regions; i++) {
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NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
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@ -1206,16 +1213,20 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
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} else {
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if (par->Architecture >= NV_ARCH_40) {
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u32 tmp;
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NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
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NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
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NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
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NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
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NV_WR32(par->PGRAPH, 0x0bc4,
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NV_RD32(par->PGRAPH, 0x0bc4) |
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0x00008000);
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tmp = NV_RD32(par->REGS, 0x1540) & 0xff;
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for(i = 0; tmp && !(tmp & 1); tmp >>= 1, i++);
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NV_WR32(par->PGRAPH, 0x5000, i);
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j = NV_RD32(par->REGS, 0x1540) & 0xff;
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if (j) {
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for (i = 0; !(j & 1); j >>= 1, i++);
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NV_WR32(par->PGRAPH, 0x5000, i);
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}
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if ((par->Chipset & 0xfff0) == 0x0040) {
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NV_WR32(par->PGRAPH, 0x09b0,
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@ -1250,6 +1261,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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case 0x0160:
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case 0x01D0:
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case 0x0240:
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case 0x03D0:
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NV_WR32(par->PMC, 0x1700,
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NV_RD32(par->PFB, 0x020C));
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NV_WR32(par->PMC, 0x1704, 0);
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@ -1269,7 +1281,6 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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0x00000108);
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break;
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case 0x0220:
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case 0x0230:
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NV_WR32(par->PGRAPH, 0x0860, 0);
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NV_WR32(par->PGRAPH, 0x0864, 0);
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NV_WR32(par->PRAMDAC, 0x0608,
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@ -1277,8 +1288,8 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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0x00100000);
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break;
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case 0x0090:
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case 0x02E0:
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case 0x0290:
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case 0x0390:
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NV_WR32(par->PRAMDAC, 0x0608,
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NV_RD32(par->PRAMDAC, 0x0608) |
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0x00100000);
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@ -1355,8 +1366,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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} else {
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if (((par->Chipset & 0xfff0) == 0x0090) ||
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((par->Chipset & 0xfff0) == 0x01D0) ||
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((par->Chipset & 0xfff0) == 0x02E0) ||
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((par->Chipset & 0xfff0) == 0x0290)) {
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((par->Chipset & 0xfff0) == 0x0290) ||
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((par->Chipset & 0xfff0) == 0x0390) ||
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((par->Chipset & 0xfff0) == 0x03D0)) {
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for (i = 0; i < 60; i++) {
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NV_WR32(par->PGRAPH,
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0x0D00 + i*4,
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@ -1407,8 +1419,8 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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} else {
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if ((par->Chipset & 0xfff0) == 0x0090 ||
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(par->Chipset & 0xfff0) == 0x01D0 ||
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(par->Chipset & 0xfff0) == 0x02E0 ||
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(par->Chipset & 0xfff0) == 0x0290) {
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(par->Chipset & 0xfff0) == 0x0290 ||
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(par->Chipset & 0xfff0) == 0x0390) {
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NV_WR32(par->PGRAPH, 0x0DF0,
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NV_RD32(par->PFB, 0x0200));
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NV_WR32(par->PGRAPH, 0x0DF4,
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@ -1495,6 +1507,12 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
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NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
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NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
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if (!state) {
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par->CurrentState = NULL;
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return;
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}
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if (par->Architecture >= NV_ARCH_10) {
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if (par->twoHeads) {
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NV_WR32(par->PCRTC0, 0x0860, state->head);
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@ -1566,6 +1584,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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VGA_WR08(par->PCIO, 0x03D5, state->interlace);
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if (!par->FlatPanel) {
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if (par->Architecture >= NV_ARCH_40)
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NV_WR32(par->PRAMDAC0, 0x0580, state->control);
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NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
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NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
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if (par->twoHeads)
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@ -1631,6 +1652,9 @@ void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
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state->scale = NV_RD32(par->PRAMDAC, 0x0848);
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state->config = NV_RD32(par->PFB, 0x0200);
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if (par->Architecture >= NV_ARCH_40 && !par->FlatPanel)
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state->control = NV_RD32(par->PRAMDAC0, 0x0580);
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if (par->Architecture >= NV_ARCH_10) {
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if (par->twoHeads) {
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state->head = NV_RD32(par->PCRTC0, 0x0860);
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@ -166,11 +166,13 @@ u8 NVReadDacData(struct nvidia_par *par)
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static int NVIsConnected(struct nvidia_par *par, int output)
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{
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volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
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u32 reg52C, reg608;
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u32 reg52C, reg608, dac0_reg608 = 0;
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int present;
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if (output)
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PRAMDAC += 0x800;
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if (output) {
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dac0_reg608 = NV_RD32(PRAMDAC, 0x0608);
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PRAMDAC += 0x800;
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}
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reg52C = NV_RD32(PRAMDAC, 0x052C);
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reg608 = NV_RD32(PRAMDAC, 0x0608);
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@ -194,8 +196,8 @@ static int NVIsConnected(struct nvidia_par *par, int output)
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else
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printk("nvidiafb: CRTC%i analog not found\n", output);
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NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) &
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0x0000EFFF);
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if (output)
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NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
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NV_WR32(PRAMDAC, 0x052C, reg52C);
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NV_WR32(PRAMDAC, 0x0608, reg608);
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@ -86,6 +86,7 @@ typedef struct _riva_hw_state {
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u32 timingV;
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u32 displayV;
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u32 crtcSync;
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u32 control;
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} RIVA_HW_STATE;
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struct riva_regs {
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@ -1195,7 +1195,8 @@ static u32 __devinit nvidia_get_chipset(struct fb_info *info)
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printk(KERN_INFO PFX "Device ID: %x \n", id);
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if ((id & 0xfff0) == 0x00f0) {
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if ((id & 0xfff0) == 0x00f0 ||
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(id & 0xfff0) == 0x02e0) {
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/* pci-e */
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id = NV_RD32(par->REGS, 0x1800);
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@ -1240,18 +1241,16 @@ static u32 __devinit nvidia_get_arch(struct fb_info *info)
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case 0x0040: /* GeForce 6800 */
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case 0x00C0: /* GeForce 6800 */
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case 0x0120: /* GeForce 6800 */
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case 0x0130:
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case 0x0140: /* GeForce 6600 */
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case 0x0160: /* GeForce 6200 */
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case 0x01D0: /* GeForce 7200, 7300, 7400 */
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case 0x02E0: /* GeForce 7300 GT */
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case 0x0090: /* GeForce 7800 */
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case 0x0210: /* GeForce 6800 */
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case 0x0220: /* GeForce 6200 */
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case 0x0230:
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case 0x0240: /* GeForce 6100 */
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case 0x0290: /* GeForce 7900 */
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case 0x0390: /* GeForce 7600 */
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case 0x03D0:
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arch = NV_ARCH_40;
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break;
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case 0x0020: /* TNT, TNT2 */
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