crypto: talitos - prepare driver for channel remap support
Add a reg member to the channel struct and use it to access channels. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Kim Phillips
Herbert Xu
parent
5b859b6ebb
commit
ad42d5fc85
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@ -99,6 +99,8 @@ struct talitos_request {
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/* per-channel fifo management */
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struct talitos_channel {
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void __iomem *reg;
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/* request fifo */
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struct talitos_request *fifo;
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@ -197,9 +199,9 @@ static int reset_channel(struct device *dev, int ch)
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struct talitos_private *priv = dev_get_drvdata(dev);
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unsigned int timeout = TALITOS_TIMEOUT;
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setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
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setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
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while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
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while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
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&& --timeout)
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cpu_relax();
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@ -209,12 +211,12 @@ static int reset_channel(struct device *dev, int ch)
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}
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/* set 36-bit addressing, done writeback enable and done IRQ enable */
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setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
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setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
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TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
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/* and ICCR writeback, if available */
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if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
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setbits32(priv->reg + TALITOS_CCCR_LO(ch),
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setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
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TALITOS_CCCR_LO_IWSE);
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return 0;
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@ -328,8 +330,9 @@ static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
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/* GO! */
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wmb();
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out_be32(priv->reg + TALITOS_FF(ch), upper_32_bits(request->dma_desc));
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out_be32(priv->reg + TALITOS_FF_LO(ch),
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out_be32(priv->chan[ch].reg + TALITOS_FF,
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upper_32_bits(request->dma_desc));
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out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
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lower_32_bits(request->dma_desc));
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spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
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@ -423,7 +426,7 @@ static u32 current_desc_hdr(struct device *dev, int ch)
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int tail = priv->chan[ch].tail;
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dma_addr_t cur_desc;
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cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
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cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
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while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
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tail = (tail + 1) & (priv->fifo_len - 1);
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@ -445,7 +448,7 @@ static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
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int i;
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if (!desc_hdr)
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desc_hdr = in_be32(priv->reg + TALITOS_DESCBUF(ch));
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desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
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switch (desc_hdr & DESC_HDR_SEL0_MASK) {
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case DESC_HDR_SEL0_AFEU:
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@ -507,8 +510,8 @@ static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
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for (i = 0; i < 8; i++)
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dev_err(dev, "DESCBUF 0x%08x_%08x\n",
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in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
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in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
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in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
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in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
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}
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/*
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@ -529,8 +532,8 @@ static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
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error = -EINVAL;
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v = in_be32(priv->reg + TALITOS_CCPSR(ch));
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v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
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v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
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v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
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if (v_lo & TALITOS_CCPSR_LO_DOF) {
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dev_err(dev, "double fetch fifo overflow error\n");
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@ -568,10 +571,10 @@ static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
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if (reset_ch) {
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reset_channel(dev, ch);
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} else {
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setbits32(priv->reg + TALITOS_CCCR(ch),
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setbits32(priv->chan[ch].reg + TALITOS_CCCR,
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TALITOS_CCCR_CONT);
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setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
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while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
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setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
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while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
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TALITOS_CCCR_CONT) && --timeout)
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cpu_relax();
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if (timeout == 0) {
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@ -2710,6 +2713,10 @@ static int talitos_probe(struct platform_device *ofdev)
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goto err_out;
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}
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for (i = 0; i < priv->num_channels; i++)
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priv->chan[i].reg = priv->reg + TALITOS_CH_BASE_OFFSET +
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TALITOS_CH_STRIDE * (i + 1);
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for (i = 0; i < priv->num_channels; i++) {
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spin_lock_init(&priv->chan[i].head_lock);
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spin_lock_init(&priv->chan[i].tail_lock);
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@ -1,7 +1,7 @@
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/*
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* Freescale SEC (talitos) device register and descriptor header defines
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*
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* Copyright (c) 2006-2010 Freescale Semiconductor, Inc.
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* Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -49,13 +49,14 @@
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#define TALITOS_ICR_LO 0x101C
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/* channel register address stride */
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#define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
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#define TALITOS_CH_STRIDE 0x100
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/* channel configuration register */
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#define TALITOS_CCCR(ch) (ch * TALITOS_CH_STRIDE + 0x1108)
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#define TALITOS_CCCR 0x8
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#define TALITOS_CCCR_CONT 0x2 /* channel continue */
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#define TALITOS_CCCR_RESET 0x1 /* channel reset */
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#define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c)
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#define TALITOS_CCCR_LO 0xc
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#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
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#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
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#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
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@ -63,8 +64,8 @@
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#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
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/* CCPSR: channel pointer status register */
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#define TALITOS_CCPSR(ch) (ch * TALITOS_CH_STRIDE + 0x1110)
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#define TALITOS_CCPSR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1114)
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#define TALITOS_CCPSR 0x10
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#define TALITOS_CCPSR_LO 0x14
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#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
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#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
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#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
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@ -79,24 +80,24 @@
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#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
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/* channel fetch fifo register */
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#define TALITOS_FF(ch) (ch * TALITOS_CH_STRIDE + 0x1148)
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#define TALITOS_FF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x114c)
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#define TALITOS_FF 0x48
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#define TALITOS_FF_LO 0x4c
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/* current descriptor pointer register */
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#define TALITOS_CDPR(ch) (ch * TALITOS_CH_STRIDE + 0x1140)
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#define TALITOS_CDPR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1144)
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#define TALITOS_CDPR 0x40
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#define TALITOS_CDPR_LO 0x44
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/* descriptor buffer register */
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#define TALITOS_DESCBUF(ch) (ch * TALITOS_CH_STRIDE + 0x1180)
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#define TALITOS_DESCBUF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1184)
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#define TALITOS_DESCBUF 0x80
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#define TALITOS_DESCBUF_LO 0x84
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/* gather link table */
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#define TALITOS_GATHER(ch) (ch * TALITOS_CH_STRIDE + 0x11c0)
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#define TALITOS_GATHER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11c4)
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#define TALITOS_GATHER 0xc0
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#define TALITOS_GATHER_LO 0xc4
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/* scatter link table */
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#define TALITOS_SCATTER(ch) (ch * TALITOS_CH_STRIDE + 0x11e0)
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#define TALITOS_SCATTER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11e4)
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#define TALITOS_SCATTER 0xe0
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#define TALITOS_SCATTER_LO 0xe4
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/* execution unit interrupt status registers */
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#define TALITOS_DEUISR 0x2030 /* DES unit */
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