mmc: sdhci-msm: Add support for UHS cards
Enabling support for ultra high speed mode cards requires some voltage switching and interaction with the PMIC via a special power IRQ. Add support for this. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -32,6 +32,21 @@
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#define CORE_POWER 0x0
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#define CORE_SW_RST BIT(7)
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#define CORE_PWRCTL_STATUS 0xdc
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#define CORE_PWRCTL_MASK 0xe0
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#define CORE_PWRCTL_CLEAR 0xe4
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#define CORE_PWRCTL_CTL 0xe8
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#define CORE_PWRCTL_BUS_OFF BIT(0)
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#define CORE_PWRCTL_BUS_ON BIT(1)
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#define CORE_PWRCTL_IO_LOW BIT(2)
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#define CORE_PWRCTL_IO_HIGH BIT(3)
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#define CORE_PWRCTL_BUS_SUCCESS BIT(0)
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#define CORE_PWRCTL_IO_SUCCESS BIT(2)
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#define REQ_BUS_OFF BIT(0)
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#define REQ_BUS_ON BIT(1)
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#define REQ_IO_LOW BIT(2)
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#define REQ_IO_HIGH BIT(3)
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#define INT_MASK 0xf
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#define MAX_PHASES 16
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#define CORE_DLL_LOCK BIT(7)
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#define CORE_DLL_EN BIT(16)
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@ -56,6 +71,7 @@
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struct sdhci_msm_host {
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struct platform_device *pdev;
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void __iomem *core_mem; /* MSM SDCC mapped address */
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int pwr_irq; /* power irq */
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struct clk *clk; /* main SD/MMC bus clock */
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struct clk *pclk; /* SDHC peripheral bus clock */
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struct clk *bus_clk; /* SDHC bus voter clock */
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@ -456,6 +472,39 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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}
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static void sdhci_msm_voltage_switch(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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u32 irq_status, irq_ack = 0;
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irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
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irq_status &= INT_MASK;
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writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
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if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))
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irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
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if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))
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irq_ack |= CORE_PWRCTL_IO_SUCCESS;
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/*
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* The driver has to acknowledge the interrupt, switch voltages and
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* report back if it succeded or not to this register. The voltage
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* switches are handled by the sdhci core, so just report success.
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*/
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writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
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}
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static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
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{
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struct sdhci_host *host = (struct sdhci_host *)data;
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sdhci_msm_voltage_switch(host);
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return IRQ_HANDLED;
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}
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static const struct of_device_id sdhci_msm_dt_match[] = {
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{ .compatible = "qcom,sdhci-msm-v4" },
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{},
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@ -469,6 +518,7 @@ static const struct sdhci_ops sdhci_msm_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
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.voltage_switch = sdhci_msm_voltage_switch,
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};
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static const struct sdhci_pltfm_data sdhci_msm_pdata = {
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@ -592,6 +642,22 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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CORE_VENDOR_SPEC_CAPABILITIES0);
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}
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/* Setup IRQ for handling power/voltage tasks with PMIC */
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msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
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if (msm_host->pwr_irq < 0) {
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dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
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msm_host->pwr_irq);
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goto clk_disable;
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}
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ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
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sdhci_msm_pwr_irq, IRQF_ONESHOT,
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dev_name(&pdev->dev), host);
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if (ret) {
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dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
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goto clk_disable;
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}
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ret = sdhci_add_host(host);
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if (ret)
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goto clk_disable;
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